"A Power-Efficient 0.5668 TOPS/W Digital Logic Accelerator Implemented ..."

Chua-Chin Wang et al. (2025)

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DOI: 10.1109/ACCESS.2025.3539760

access: open

type: Journal Article

metadata version: 2025-03-03

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Chua-Chin Wang, Shih-Heng Luo, Hsin-Che Wu, Ralph Gerard B. Sangalang, Chewnpu Jou, Harry Hsia, Lan-Chou Cho:
A Power-Efficient 0.5668 TOPS/W Digital Logic Accelerator Implemented Using 40-nm CMOS Process for Underwater Object Recognition Usage. IEEE Access 13: 28123-28134 (2025)

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