"A Lock Detector Loop for Low-power PLL-Based Clock and Data Recovery Circuits."

Chua-Chin Wang et al. (2018)

> Home

Details and statistics

DOI: 10.1007/S00034-017-0621-7

access: closed

type: Journal Article

metadata version: 2022-04-09

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/cssp/WangHCS18
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/cssp/WangHCS18
Chua-Chin Wang, Zong-You Hou, Chih-Lin Chen, Doron Shmilovitz:
A Lock Detector Loop for Low-power PLL-Based Clock and Data Recovery Circuits. Circuits Syst. Signal Process. 37(4): 1692-1703 (2018)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.