"A comprehensive analysis of the impact of sub 10-nm CNFET technology on ..."

Chenlin Shi et al. (2026)

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DOI: 10.1016/J.VLSI.2025.102583

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type: Journal Article

metadata version: 2025-12-07

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Chenlin Shi, Tongxin Yang, Ryota Shioya, Hayato Yamaki, Hiroki Honda, Shinobu Miwa:
A comprehensive analysis of the impact of sub 10-nm CNFET technology on 64-bit parallel prefix adders and 32-bit matrix multiply units. Integr. 106: 102583 (2026)

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