"Process Variation Aware Transistor Sizing for Load Balance of Multiple ..."

Kumar Yelamarthi, Chien-In Henry Chen (2008)

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DOI: 10.4304/JCP.3.2.21-28

access: open

type: Journal Article

metadata version: 2021-02-25

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Kumar Yelamarthi, Chien-In Henry Chen:
Process Variation Aware Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization. J. Comput. 3(2): 21-28 (2008)

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