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2020 – today
- 2021
[j27]Yu Wang
, Jianfeng Ren, Chien-In Henry Chen:
Calibration of optimized minimum inductor bandpass filter with controllable bandwidth and stopband rejection. Integr. 81: 300-312 (2021)- 2020
- [j26]Feiran Liu, Chien-In Henry Chen:
High two-signal dynamic range and accurate frequency measurement for close frequency separation wideband digital receiver using adaptive gain control and adaptive thresholding. Integr. 72: 72-81 (2020)
2010 – 2019
- 2017
- [j25]Yu Wang, Jian Chen, Chien-In Henry Chen:
Chebyshev Bandpass Filter Using Resonator of Tunable Active Capacitor and Inductor. VLSI Design 2017: 5369167:1-5369167:12 (2017) - 2016
- [j24]Stephen Benson, Chien-In Henry Chen, David M. Lin, Lihyeh L. Liou:
Digital linear chirp receiver for high chirp rates with high resolution time-of-arrival and time-of-departure estimation. IEEE Trans. Aerosp. Electron. Syst. 52(3): 1146-1154 (2016) - 2015
- [j23]Jian Chen, Chien-In Henry Chen:
Process Variation Aware Wide Tuning Band Pass Filter for Steep Roll-Off High Rejection. VLSI Design 2015: 408035:1-408035:9 (2015) - 2014
- [c20]Kiran George, Chien-In Henry Chen:
Modular test RF instrumentation and measurement for a hybrid computing digital wideband receiver. I2MTC 2014: 352-356 - 2013
- [j22]Kiran George, Chien-In Henry Chen:
Multiple Signal Detection Digital Wideband Receiver using Hardware Accelerators. IEEE Trans. Aerosp. Electron. Syst. 49(2): 706-715 (2013) - 2011
- [j21]Stephen Benson, Chien-In Henry Chen:
Adaptive Thresholding for High Dual-Tone Signal Instantaneous Dynamic Range in Digital Microwave Receiver. IEEE Trans. Instrum. Meas. 60(5): 1869-1875 (2011) - [j20]Kiran George, Chien-In Henry Chen:
A Hybrid Computing Platform Digital Wideband Receiver Design and Performance Measurement. IEEE Trans. Instrum. Meas. 60(12): 3956-3958 (2011) - [c19]Kumar Yelamarthi, Chien-In Henry Chen:
Delay optimization considering power saving in dynamic CMOS circuits. ISQED 2011: 364-369 - 2010
- [j19]Kumar Yelamarthi, Chien-In Henry Chen:
Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations. VLSI Design 2010: 230783:1-230783:13 (2010)
2000 – 2009
- 2009
- [j18]Kiran George, Chien-In Henry Chen:
Logic Built-In Self-Test for Core-Based Designs on System-on-a-Chip. IEEE Trans. Instrum. Meas. 58(5): 1495-1504 (2009) - [j17]Yu-Heng George Lee, Chien-In Henry Chen:
Dynamic Kernel Function Fast Fourier Transform With Variable Truncation Scheme for Wideband Coarse Frequency Detection. IEEE Trans. Instrum. Meas. 58(5): 1555-1562 (2009) - [c18]Yu-Heng George Lee, Chien-In Henry Chen:
Dual Thresholding for Digital Wideband Receivers with Variable Truncation Scheme. ISCAS 2009: 920-923 - 2008
- [j16]Kumar Yelamarthi, Chien-In Henry Chen:
Process Variation Aware Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization. J. Comput. 3(2): 21-28 (2008) - [j15]Xinhui Zhang, Chien-In Henry Chen, Arvindkumar Chakravarthy:
Structure Design and Optimization of 2-D LFSR-Based Multisequence Test Generator in Built-In Self-Test. IEEE Trans. Instrum. Meas. 57(3): 651-663 (2008) - [c17]Yu-Heng George Lee, James Helton, Chien-In Henry Chen:
Real-time FPGA-based implementation of digital instantaneous frequency measurement receiver. ISCAS 2008: 2494-2497 - [c16]Kumar Yelamarthi, Chien-In Henry Chen:
Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic. ISQED 2008: 143-147 - [c15]James Helton, Chien-In Henry Chen, David M. Lin, James B. Y. Tsui:
FPGA-Based 1.2 GHz Bandwidth Digital Instantaneous Frequency Measurement Receiver. ISQED 2008: 568-571 - 2007
- [j14]Mingzhen Wang, Chien-In Henry Chen, Shailesh Radhakrishnan:
Low-Power 4-b 2.5-GSPS Pipelined Flash Analog-to-Digital Converter in 130-nm CMOS. IEEE Trans. Instrum. Meas. 56(3): 1064-1073 (2007) - [j13]Jason Wibbenmeyer, Chien-In Henry Chen:
Built-In Self-Test for Low-Voltage High-Speed Analog-to-Digital Converters. IEEE Trans. Instrum. Meas. 56(6): 2748-2756 (2007) - [c14]Kumar Yelamarthi, Chien-In Henry Chen:
Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization. ISQED 2007: 426-431 - [c13]Mingzhen Wang, Chien-In Henry Chen:
Low-power 1.25-GHZ signal bandwidth 4-bit CMOS analog-to-digital converter for high spurious-free dynamic range wideband communications. SoCC 2007: 109-112 - 2005
- [j12]Chien-In Henry Chen, Kiran George, William McCormick, James B. Y. Tsui, Stephen L. Hary, Keith M. Graves:
Design and performance evaluation of a 2.5-GSPS digital receiver. IEEE Trans. Instrum. Meas. 54(3): 1089-1099 (2005) - [c12]Shailesh Radhakrishnan, Mingzhen Wang, Chien-In Henry Chen:
A low-power 4-b 2.5 Gsample/s pipelined flash analog-to-digital converter using differential comparator and DCVSPG encoder. ISCAS (6) 2005: 6142-6145 - 2004
- [j11]Chien-In Henry Chen, Kiran George:
Configurable two-dimensional linear feedback shifter registers for parallel and serial built-in self-test. IEEE Trans. Instrum. Meas. 53(4): 1005-1014 (2004) - 2003
- [c11]Chien-In Henry Chen, Kiran George:
Configurable two-dimensional linear feedback shifter registers for deterministic and random patterns [logic BIST]. ISCAS (5) 2003: 521-524 - [c10]Chien-In Henry Chen, Kiran George:
Automated Synthesis of Configurable Two-dimensional Linear Feedback Shifter Registers for Random/Embedded Test Patterns. ISQED 2003: 111-116 - 2002
- [j10]Chien-In Henry Chen, Mahesh Wagh:
Testability Synthesis for Jumping Carry Adders. VLSI Design 14(2): 155-169 (2002) - [j9]Chien-In Henry Chen:
Timing Analysis and Optimization for DSM IC - Guest Editorial. VLSI Design 15(3): 555-556 (2002) - [j8]Ichiang Lin, Chien-In Henry Chen:
Timing Challenges for Very Deep Sub-Micron (VDSM) IC. VLSI Design 15(3): 557-562 (2002) - [j7]Johnnie A. Huang, Chien-In Henry Chen:
Timing-Driven-Testable Convergent Tree Adders. VLSI Design 15(3): 637-645 (2002) - 2001
- [c9]Chien-In Henry Chen:
Synthesis of configurable linear feedback shifter registers for detecting random-pattern-resistant faults. ISSS 2001: 203-208 - 2000
- [j6]Chien-In Henry Chen, Yingjie Zhou:
Configurable 2-D Linear Feedback Shift Registers for VLSI Built-in Self-test Designs. VLSI Design 11(2): 149-159 (2000)
1990 – 1999
- 1999
- [c8]Meghanad D. Wagh, Chien-In Henry Chen:
High-level design synthesis with redundancy removal for high speed testable adders. ISCAS (6) 1999: 358-361 - 1994
- [j5]Chien-In Henry Chen, Anup Kumar:
Comments on "Area-Time Optimal Adder Design". IEEE Trans. Computers 43(4): 507-512 (1994) - [j4]Chien-In Henry Chen, Joel T. Yuen:
Automated synthesis of pseudo-exhaustive test generator in VLSI BIST design. IEEE Trans. Very Large Scale Integr. Syst. 2(3): 273-291 (1994) - [j3]Chien-In Henry Chen, Gerald E. Sobelman:
Cluster Partitioning Techniques for Data Path Synthesis. VLSI Design 1(3): 181-192 (1994) - [j2]Chien-In Henry Chen:
Using PDM on Multiport Memory Allocation in Data Path. VLSI Design 1(3): 217-232 (1994) - [j1]Chien-In Henry Chen:
Partitioning Techniques for Built-In Self-Test Design. VLSI Design 2(3): 185-198 (1994) - 1993
- [c7]Chien-In Henry Chen, Joel T. Yuen:
Logic partitioning to pseudo-exhaustive test for BIST design. ICCAD 1993: 646-649 - 1992
- [c6]Chien-In Henry Chen, Joel T. Yuen:
Concurrent Test Scheduling in Built-In Self-Test Environment. ICCD 1992: 256-259 - [c5]Chien-In Henry Chen, Joel T. Yuen, Ji-Der Lee:
Autonomous-Tol for Hardware Partitioning in a Built-in Self-Test Environment. ICCD 1992: 264-267 - 1991
- [c4]Chien-In Henry Chen:
Graph Partitioning for Concurrent Test Scheduling in VLSI Circuit. DAC 1991: 287-290 - [c3]Chien-In Henry Chen:
BISTSYN - A Built-In Self-Test Synthesizer. ICCAD 1991: 240-243 - [c2]Chien-In Henry Chen:
Allocation of Multiport Memory with Ports of Different Type in Register Transfer Level Synthesis. ICCD 1991: 418-421
1980 – 1989
- 1989
- [c1]Chien-In Henry Chen, Gerald E. Sobelman:
An efficient approach to pseudo-exhaustive test generation for BIST design. ICCD 1989: 576-579
Coauthor Index
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