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"A New Current Profile Determination Methodology Incorporating Gating Logic ..."
Nivedita Laskar et al. (2018)
- Nivedita Laskar, Suman Debnath, Alak Majumder, Bidyut K. Bhattacharyya:
A New Current Profile Determination Methodology Incorporating Gating Logic to Minimize the Noise of CPU Chip by 40%. J. Circuits Syst. Comput. 27(3): 1850049:1-1850049:20 (2018)
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