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"A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring ..."

John Barth et al. (2008)

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DOI: 10.1109/JSSC.2007.908006

access: closed

type: Journal Article

metadata version: 2022-03-02

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John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer:
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier. IEEE J. Solid State Circuits 43(1): 86-95 (2008)

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