Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"A clock generator with cascaded dynamic frequency counting loops for wide ..."

Pao-Lung Chen et al. (2006)

> Home

Details and statistics

DOI: 10.1109/JSSC.2006.874273

access: closed

type: Journal Article

metadata version: 2022-01-03

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/ChenCYL06
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/ChenCYL06
Pao-Lung Chen, Ching-Che Chung, Jyh-Neng Yang, Chen-Yi Lee:
A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications. IEEE J. Solid State Circuits 41(6): 1275-1285 (2006)

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.