default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDIEEE Journal of Solid-State Circuits, Volume 41
Volume 41, Number 1, January 2006
- Jan Van der Spiegel, Ram K. Krishnamurthy, Sreedhar Natarajan, Chih-Kong Ken Yang:
Introduction to the Special Issue on the 2005 IEEE International Solid-State Circuits Conference. 3-6 - Marc-Alexandre Dubois, Jean-François Carpentier, Pierre Vincent, Christophe Billard, Guy Parat, Claude Müller, Pascal Ancey, Patrick Conti:
Monolithic above-IC resonator technology for integrated architectures in mobile and wireless communication. 7-16 - Behzad Razavi:
A 60-GHz CMOS receiver front-end. 17-22 - Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Takayasu Sakurai, Tadahiro Kuroda:
A 195-gb/s 1.2-W inductive inter-chip wireless superconnect with transmit power control scheme for 3-D-stacked system in a package. 23-34 - Toshiyuki Umeda, Hiroshi Yoshida, Shuichi Sekine, Yumi Fujita, Takuji Suzuki, Shoji Otaka:
A 950-MHz rectifier circuit for sensor network tags with 10-m distance. 35-41 - Glenn E. R. Cowan, Robert C. Melville, Yannis P. Tsividis:
A VLSI analog computer/digital computer accelerator. 42-53 - Toshihide Fujiyoshi, Shinichiro Shiratake, Shuou Nomura, Tsuyoshi Nishikawa, Yoshiyuki Kitasho, Hideho Arakida, Yuji Okuda, Yoshiro Tsuboi, Mototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Fumitoshi Hatori, Takayoshi Shimazawa, Kunihiko Yahagi, Hideki Takeda, Masami Murakata, Fumihiro Minami, Naoyuki Kawabe, Takeshi Kitahara, Katsuhiro Seta, Masafumi Takahashi, Yukihito Oowaki, Tohru Furuyama:
A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling. 54-62 - Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia Melitta Müller, Osamu Takahashi, A. Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, Vandung To, Eiji Iwata:
The microarchitecture of the synergistic processor for a cell processor. 63-70 - Donghyun Kim, Kyusik Chung, Chang-Hyo Yu, Chun-Ho Kim, Inho Lee, Jaewan Bae, Young-Jun Kim, Jae-Hyeon Park, Sungbeen Kim, Yong-Ha Park, Nak Hee Seong, Jin-Aeon Lee, Jaehong Park, Stephen Oh, Seh-Woong Jeong, Lee-Sup Kim:
An SoC with 1.3 gtexels/s 3-D graphics full pipeline for consumer applications. 71-84 - Andrea Lodi, Andrea Cappelli, Massimo Bocchi, Claudio Mucci, Massimilano Innocenti, Claudia De Bartolomeis, Luca Ciccarelli, Roberto Giansante, Antonio Deledda, Fabio Campi, Mario Toma, Roberto Guerrieri:
XiSystem: a XiRisc-based SoC with reconfigurable IO module. 85-96 - Andrew Cofler, Francois Druilhe, Denis Dutoit
, Michel Harrand:
A reprogrammable EDGE baseband and multimedia handset SoC with 6-mbit embedded DRAM. 97-106 - Satoru Akiyama, Tomonori Sekiguchi, Kazuhiko Kajigaya, Satoru Hanzawa, Riichiro Takemura, Takayuki Kawahara:
Concordant memory design: an integrated statistical design approach for multi-gigabit DRAM. 107-112 - Koichi Takeda, Yasuhiko Hagihara, Yoshiharu Aimoto, Masahiro Nomura, Yoetsu Nakazawa, Toshio Ishii, Hiroyuki Kobatake:
A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications. 113-121 - Hyung-Rok Oh, Beak-Hyung Cho, Woo Yeong Cho, Sangbeom Kang, Byung-Gil Choi, Hye-Jin Kim, Ki-Sung Kim, Du-Eung Kim, Choong-Keun Kwak, Hyun-Geun Byun, Gitae Jeong, Hong-Sik Jeong, Kinam Kim:
Enhanced write performance of a 64-mb phase-change random access memory. 122-126 - Kyu-Hyoun Kim, Young-Soo Sohn, Chan-Kyoung Kim, Moon-Sook Park, Dong-Jin Lee, Woo-Seop Kim, Changhyun Kim:
A 20-gb/s 256-mb DRAM with an inductorless quadrature PLL and a cascaded pre-emphasis transmitter. 127-134 - Takashi Ohsawa, Katsuyuki Fujita, Kosuke Hatsuda, Tomoki Higashi, Tomoaki Shino, Yoshihiro Minami, Hiroomi Nakajima, Mutsuo Morikado, Kazumi Inoh, Takeshi Hamamoto, Shigeyoshi Watanabe, Shuso Fujii, Tohru Furuyama:
Design of a 128-mb SOI DRAM using the floating body cell (FBC). 135-145 - Kevin Zhang, Uddalak Bhattacharya, Zhanping Chen, Fatih Hamzaoglu, Daniel Murray, Narendra Vallepalli, Yih Wang, Bo Zheng, Mark Bohr:
A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply. 146-151 - Toshikazu Suzuki, Yoshinobu Yamagami, Ichiro Hatanaka, Akinori Shibayama, Hironori Akamatsu, Hiroyuki Yamauchi:
A sub-0.5-V operating embedded SRAM featuring a multi-bit-error-immune hidden-ECC scheme. 152-160 - Takahiko Hara, Koichi Fukuda, Kazuhisa Kanazawa, Noboru Shibata, Koji Hosono, Hiroshi Maejima, Michio Nakagawa, Takumi Abe, Masatsugu Kojima, Masaki Fujiu, Yoshiaki Takeuchi, Kazumi Amemiya, Midori Morooka, Teruhiko Kamei, Hiroaki Nasu, Chi-Ming Wang, Kiyofumi Sakurai, Naoya Tokiwa, Hiroko Waki, Tohru Maruyama, Susumu Yoshikawa, Masaaki Higashitani, Tuan D. Pham, Yupin Fong, Toshiharu Watanabe:
A 146-mm2 8-gb multi-level NAND flash memory with 70-nm CMOS technology. 161-169 - Chris Hyung-Il Kim, Jae-Joon Kim, Ik-Joon Chang, Kaushik Roy:
PVT-aware leakage reduction for on-die caches with improved read stability. 170-178 - Dac C. Pham, Tony Aipperspach, David Boerstler, Mark Bolliger, Rajat Chaudhry, Dennis Cox, Paul E. Harvey, H. Peter Hofstee, Charles R. Johns, Jim Kahle, Atsushi Kameyama, John M. Keaty, Yoshio Masubuchi, Mydung Pham, Jürgen Pille, Stephen D. Posluszny, Mack W. Riley, Daniel L. Stasiak, Masakazu Suzuoki, Osamu Takahashi, James D. Warnock, Stephen Weitzel, Dieter F. Wendel, Kazuaki Yazawa:
Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor. 179-196 - Samuel Naffziger, Blaine A. Stackhouse, Tom Grutkowski, Doug Josephson, Jayen Desai, Elad Alon, Mark Horowitz:
The implementation of a 2-core, multi-threaded itanium family processor. 197-209 - Jason M. Hart, Kyung T. Lee, Dennis Chen, Lik Cheng, Chipai Chou, Anand Dixit, Dale Greenley, Gregory Gruber, Kenneth Ho, Jesse Hsu, Naveen G. Malur, John Wu:
Implementation of a fourth-generation 1.8-GHz dual-core SPARC V9 microprocessor. 210-217 - Tim C. Fischer, Jayen Desai, Bruce Andrew Doyle, Samuel Naffziger, Ben Patella:
A 90-nm variable frequency clock system for a power-managed itanium architecture processor. 218-228 - Rich McGowen, Christopher Poirier, Chris Bostak, Jim Ignowski, Mark Millican, Warren H. Parks, Samuel Naffziger:
Power and temperature control on a 90-nm Itanium family processor. 229-237 - Benton H. Calhoun, Anantha P. Chandrakasan:
Ultra-dynamic Voltage scaling (UDVS) using sub-threshold operation and local Voltage dithering. 238-245 - Eric S. Fetzer, David M. Dahle, Casey Little, Kevin Safford:
The Parity protected, multithreaded register files on the 90-nm itanium microprocessor. 246-255 - Steven K. Hsu, Sanu K. Mathew, Mark A. Anders, Bart R. Zeydel, Vojin G. Oklobdzija, Ram K. Krishnamurthy, Shekhar Y. Borkar:
A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS. 256-264 - Li-min Lee, Daniel Weinlader, Chih-Kong Ken Yang:
A sub-10-ps multiphase sampling system using redundancy. 265-273 - Daehyun Chung, Chunghyun Ryu, Hyungsoo Kim, Choonheung Lee, Jinhan Kim, Kicheol Bae, Jiheon Yu, Hoi-Jun Yoo, Joungho Kim:
Chip-package hybrid clock distribution network and DLL for low jitter clock delivery. 274-286 - Lei Luo, John M. Wilson, Stephen E. Mick, Jian Xu, Liang Zhang, Paul D. Franzon:
3 gb/s AC coupled chip-to-chip communication using a low swing pulse receiver. 287-296 - Daniël Schinkel, Eisse Mensink, Eric A. M. Klumperink, Ed J. M. van Tuijl, Bram Nauta:
A 3-Gb/s/ch transceiver for 10-mm uninterrupted RC-limited global on-chip interconnects. 297-306
Volume 41, Number 2, February 2006
- Aida Varzaghani, Chih-Kong Ken Yang:
A 600-MS/s 5-bit pipeline A/D converter using digital reference calibration. 310-319 - Jurgen Deveugele, Michiel S. J. Steyaert:
A 10-bit 250-MS/s binary-weighted current-steering DAC. 320-329 - Nikolaus Klemmer, Emad Hegazi:
A DLL-biased, 14-bit DS analog-to-digital converter for GSM/GPRS/EDGE handsets. 330-338 - Jesús Arias Álvarez, Peter Kiss, Vladimir I. Prodanov, Vito Boccuzzi, Mihai Banu, David Bisbal, Jacinto San Pablo, Luis Quintanilla, Juan Barbolla:
A 32-mW 320-MHz continuous-time complex delta-sigma ADC for multi-mode wireless-LAN receivers. 339-351 - Haluk Külah, Junseok Chae, Navid Yazdi, Khalil Najafi:
Noise analysis and characterization of a sigma-delta capacitive microaccelerometer. 352-361 - Jim Kulyk, James W. Haslett:
A monolithic CMOS 2368±30 MHz transformer based Q-enhanced series-C coupled resonator bandpass filter. 362-374 - Tadashi Maeda, Hitoshi Yano, Shinichi Hori, Noriaki Matsuno, Tomoyuki Yamase, Takashi Tokairin, Robert Walkington, Nobuhide Yoshida, Keiichi Numata, Kiyoshi Yanagisawa, Yuji Takahashi, Masahiro Fujii, Hikaru Hida:
Low-power-consumption direct-conversion CMOS transceiver for multi-standard 5-GHz wireless LAN systems with channel bandwidths of 5-20 MHz. 375-383 - Pete Sivonen, Jussi Tervaluoto, Niko Mikkola, Aarno Pärssinen:
A 1.2-V RF front-end with on-chip VCO for PCS 1900 direct conversion receiver in 0.13-μm CMOS. 384-394 - Imtinan Elahi, Khurram Muhammad, Poras T. Balsara:
I/Q mismatch compensation using adaptive decorrelation in a low-IF receiver in 90-nm CMOS process. 395-404 - Curtis Leifso, John Nisbet:
A monolithic 6 GHz quadrature frequency doubler with adjustable phase offset. 405-412 - Elad Alon, Jaeha Kim, Sudhakar Pamarti, Ken Chang, Mark Horowitz:
Replica compensated linear regulators for supply-regulated phase-locked loops. 413-424 - Jae-Youl Lee, Sung-Eun Kim, Seong-Jun Song, Jin-Kyung Kim, Sunyoung Kim, Hoi-Jun Yoo:
A regulated charge pump with small ripple voltage and fast start-up. 425-432 - Krishnakumar Sundaresan, Phillip E. Allen, Farrokh Ayazi:
Process and temperature compensation in a 7-MHz CMOS clock oscillator. 433-442 - Ethan Crain, Michael H. Perrott:
A 3.125 Gb/s limit amplifier in CMOS with 42 dB gain and 1 μs offset compensation. 443-451 - Hideki Kamitsuna, Yasuro Yamane, Masami Tokumitsu, Hirohiko Sugahara, Masahiro Muraguchi:
Low-power InP-HEMT switch ICs integrating miniaturized 2×2 switches for 10-Gb/s systems. 452-460 - Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III, Dale Edwards:
A 16 Gb/s adaptive bandwidth on-chip bus based on hybrid current/voltage mode signaling. 461-473 - Weize Xu, Eby G. Friedman:
On-chip test circuit for measuring substrate and line-to-line coupling noise. 474-482 - Guichang Zhong, Fan Xu, Alan N. Willson Jr.:
A power-scalable reconfigurable FFT/IFFT IC based on a multi-processor ring. 483-495 - Meng-Fan Chang, Lih-Yih Chiou, Kuei-Ann Wen:
A full code-patterns coverage high-speed embedded ROM using dynamic virtual guardian technique. 496-506 - Sami Karvonen, Thomas A. D. Riley, Sami Kurtti, Juha Kostamovaara:
A quadrature charge-domain sampler with embedded FIR and IIR filtering functions. 507-515
Volume 41, Number 3, March 2006
- Bo Xia, Alberto Valdes-Garcia, Edgar Sánchez-Sinencio:
A 10-bit 44-MS/s 20-mW configurable time-interleaved pipeline ADC for a dual-mode 802.11b/Bluetooth receiver. 530-539 - Giuseppe Gramegna, Philip G. Mattos, Marco Losi, Sabyasachi Das, Massimo Franciotta, Nino G. Bellantone, Michele Vaiana, Valentina Mandará, Mario Paparo:
A 56-mW 23-mm2 single-chip 180-nm CMOS GPS receiver with 27.2-mW 4.1-mm2 radio. 540-551 - Massimo Brandolini, Paolo Rossi, Davide Sanzogni, Francesco Svelto:
A +78 dBm IIP2 CMOS direct downconversion mixer for fully integrated UMTS receivers. 552-559 - Jonathan P. Comeau, John D. Cressler:
A 28-GHz SiGe up-conversion mixer using a series-connected triplet for higher dynamic range and improved IF port return loss. 560-565 - Jri Lee:
A 3-to-8-GHz fast-hopping frequency synthesizer in 0.18-μm CMOS technology. 566-573 - Scott Hazenboom, Terri S. Fiez, Kartikeya Mayaram:
A comparison of substrate noise coupling in lightly and heavily doped CMOS processes for 2.4-GHz LNAs. 574-587 - Sotir Ouzounov, Engel Roza, Johannes A. Hegt, Gerard van der Weide, Arthur H. M. van Roermund:
Analysis and design of high-performance asynchronous sigma-delta Modulators with a binary quantizer. 588-596 - Mike Yun He, John Poulton:
A CMOS mixed-signal clock and data recovery circuit for OIF CEI-6G+ backplane transceiver. 597-606 - James F. Buckwalter, Ali Hajimiri:
Analysis and equalization of data-dependent jitter. 607-620 - James F. Buckwalter, Ali Hajimiri:
Cancellation of crosstalk-induced jitter. 621-632 - Seok-Woo Choi, Hyun-Bae Lee, Hong-June Park:
A three-data differential signaling over four conductors with pre-emphasis and equalization: a CMOS current mode implementation. 633-641 - Yoshiaki Konno, Koji Tomioka, Yusuke Aiba, Katsuhiko Yamazoe, Bang-Sup Song:
A CMOS 1×-16× speed DVD write channel IC. 642-650 - Helmy Eltoukhy, Khaled N. Salama, Abbas El Gamal:
A 0.18-μm CMOS bioluminescence detection lab-on-chip. 651-662 - Abhishek Bandyopadhyay, Jungwon Lee, Ryan W. Robucci, Paul E. Hasler:
MATIA: a programmable 80 WμW/frame CMOS block matrix transform imager architecture. 663-672 - Mladen Panovic, Andreas Demosthenous:
A low-power analog motion estimation processor for digital video coding. 673-683 - Mohammad M. Mansour, Naresh R. Shanbhag:
A 640-Mb/s 2048-bit programmable LDPC decoder chip. 684-698 - Matthew B. Leslie, R. Jacob Baker:
Noise-shaping sense amplifier for MRAM cross-point arrays. 699-704 - Masanao Yamaoka, Noriaki Maeda, Yoshihiro Shinozaki, Yasuhisa Shimazaki, Koji Nii, Shigeru Shimada, Kazumasa Yanagisawa, Takayuki Kawahara:
90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique. 705-711 - Kostas Pagiamtzis, Ali Sheikholeslami:
Content-addressable memory (CAM) circuits and architectures: a tutorial and survey. 712-727 - Nobutaro Shibata, Hiroshi Kiya, Shigehiro Kurita, Hidetaka Okamoto, Masa'aki Tan'no, Takakuni Douseki:
A 0.5-V 25-MHz 1-mW 256-kb MTCMOS/SOI SRAM for solar-power-operated portable personal digital equipment - sure write operation by using step-down negatively overdriven bitline scheme. 728-742
Volume 41, Number 4, April 2006
- Keng L. Wong, Tawfik Rahal-Arabi, Matthew Ma, Greg Taylor:
Enhancing microprocessor immunity to power supply noise with clock-data compensation. 749-758 - Hwa-Joon Oh, Silvia M. Müller, Christian Jacobi, Kevin D. Tran, Scott R. Cottier, Brad W. Michael, Hiroo Nishikawa, Yonetaro Totsuka, Tatsuya Namatame, Naoka Yano, Takashi Machida, Sang H. Dhong:
A fully pipelined single-precision floating-point unit in the synergistic processor element of a CELL processor. 759-771 - Anup P. Jose, George Patounakis, Kenneth L. Shepard:
Pulsed current-mode signaling for nearly speed-of-light intrachip communication. 772-780 - David D. Hwang, Kris Tiri, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede:
AES-Based Security Coprocessor IC in 0.18-$muhbox m$CMOS With Resistance to Differential Power Analysis Side-Channel Attacks. 781-792 - Shidhartha Das, David Roberts, Seokwoo Lee, Sanjay Pant, David T. Blaauw, Todd M. Austin, Krisztián Flautner, Trevor N. Mudge:
A self-tuning DVS processor using delay-error detection and correction. 792-804 - Masahiro Nomura, Yoshifumi Ikenaga, Koichi Takeda, Yoetsu Nakazawa, Yoshiharu Aimoto, Yasuhiko Hagihara:
Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes. 805-814 - Yasuhisa Takeyama, Hiroyuki Otake, Osamu Hirabayashi, Keiichi Kushida, Nobuaki Otsuka:
A low leakage SRAM macro with replica cell biasing scheme. 815-822 - Kyomin Sohn, Hyun-Sun Mo, Young-Ho Suh, Hyun-Geun Byun, Hoi-Jun Yoo:
An autonomous SRAM with on-chip sensors in an 80-nm double stacked cell technology. 823-830 - Churoo Park, Hoeju Chung, Yun-Sang Lee, Jaekwan Kim, JaeJun Lee, Moo Sung Chae, Dae-Hee Jung, Sung-Ho Choi, Seung-young Seo, Taek-Seon Park, Jun-Ho Shin, Jin-Hyung Cho, Seunghoon Lee, Ki-Whan Song, Kyu-Hyoun Kim, Jung-Bae Lee, Changhyun Kim, Soo-In Cho:
A 512-mb DDR3 SDRAM prototype with CIO minimization and self-calibration techniques. 831-838 - Fa Foster Dai, Weining Ni, Yin Shi, Richard C. Jaeger:
A direct digital frequency synthesizer with fourth-order phase domain ΔΣ noise shaper and 12-bit current-steering DAC. 839-850 - Nana Akahane, Shigetoshi Sugawa, Satoru Adachi, Kazuya Mori, Toshiyuki Ishiuchi, Koichi Mizobuchi:
A sensitivity and linearity improvement of a 100-dB dynamic range CMOS image sensor using a lateral overflow integration capacitor. 851-858 - Koichi Ishida, Kouichi Kanda, Atit Tamtrakarn, Hiroshi Kawaguchi, Takayasu Sakurai:
Managing subthreshold leakage in charge-based analog circuits with low-VTH transistors by analog T- switch (AT-switch) and super cut-off CMOS (SCCMOS). 859-867 - Andrew Chang, David K. Su, Richard K. Hester, Bruce A. Wooley:
A CMOS oversampled DAC with multi-bit semi-digital filtering and boosted subcarrier SNR for ADSL central office modems. 868-875 - Sunyoung Kim, Jae-Youl Lee, Seong-Jun Song, Namjun Cho, Hoi-Jun Yoo:
An energy-efficient analog front-end circuit for a sub-1-V digital hearing aid chip. 876-882 - Kunihiko Iizuka, Hirofumi Matsui, Masaya Ueda, Mutsuo Daito:
A 14-bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40 MS/s. 883-890 - Takahide Terada, Shingo Yoshizumi, Muhammad Muqsith, Yukitoshi Sanada, Tadahiro Kuroda:
A CMOS ultra-wideband impulse radio transceiver for 1-mb/s data communications and ±2.5-cm range finding. 891-898 - Jaeha Kim, Jeong-Kyoum Kim, Bong-Joon Lee, Namhoon Kim, Deog-Kyoon Jeong, Wonchan Kim:
A 20-GHz phase-locked loop for 40-gb/s serializing transmitter in 0.13-μm CMOS. 899-908 - Jonathan Sewter, Anthony Chan Carusone:
A CMOS finite impulse response filter with a crossover traveling wave topology for equalization up to 30 Gb/s. 909-917 - (Withdrawn) Notice of Violation of IEEE Publication Principles: A multi-rate 9.953-12.5-GHz 0.2-μm SiGe BiCMOS LC oscillator using a resistor-tuned varactor and a supply pushing cancellation circuit. 918-934
- Aida Varzaghani, Chih-Kong Ken Yang:
A 6-GSamples/s multi-level decision feedback equalizer embedded in a 4-bit time-interleaved pipeline A/D converter. 935-944 - Tae Wook Kim, Bonkee Kim:
A 13-dB IIP3 improved low-power CMOS RF programmable gain amplifier using differential circuit transconductance linearization for various terrestrial mobile D-TV applications. 945-953 - Thomas Toifl, Christian Menolfi, Michael Ruegg, Robert Reutemann, Peter Buchmann, Marcel A. Kossel, Thomas Morf, Jonas R. M. Weiss, Martin L. Schmatz:
A 22-gb/s PAM-4 receiver in 90-nm CMOS SOI technology. 954-965 - Scott E. Meninger, Michael H. Perrott:
A 1-MHZ bandwidth 3.6-GHz 0.18-μm CMOS fractional-N synthesizer utilizing a hybrid PFD/DAC structure for reduced broadband phase noise. 966-980 - Antonio Liscidini, Massimo Brandolini, Davide Sanzogni, Rinaldo Castello:
A 0.13 μm CMOS front-end, for DCS1800/UMTS/802.11b-g with multiband positive feedback low-noise amplifier. 981-989 - Jan H. Rutger Schrader, Eric A. M. Klumperink, Jan L. Visschers, Bram Nauta:
Pulse-width modulation pre-emphasis applied in a wireline transmitter, achieving 33 dB loss compensation at 5-Gb/s in 0.13-μm CMOS. 990-999
Volume 41, Number 5, May 2006
- Jri Lee:
High-speed circuit designs for transmitters in broadband data links. 1004-1015 - Ruiyuan Zhang, George S. La Rue:
Fast acquisition clock and data recovery circuit with low jitter. 1016-1024 - Day-Uei Li, Chia-Ming Tsai:
10-Gb/s modulator drivers with local feedback networks. 1025-1030 - Ari Yakov Valero-López, Sung Tae Moon, Edgar Sánchez-Sinencio:
Self-calibrated quadrature generator for WLAN multistandard frequency synthesizer. 1031-1041 - Jinho Jeong, Youngwoo Kwon:
A fully integrated V-band PLL MMIC using 0.15-μm GaAs pHEMT technology. 1042-1050 - Hsiang-Hui Chang, Jung-Yu Chang, Chun-Yi Kuo, Shen-Iuan Liu:
A 0.7-2-GHz self-calibrated multiphase delay-locked loop. 1051-1061 - Michiel De Wilde, Wim Meeus, Pieter Rombouts, Jan Van Campenhout:
A simple on-chip repetitive sampling setup for the quantification of substrate noise. 1062-1072 - Jongchan Kang, Daekyu Yu, Youngoo Yang, Bumman Kim:
Highly linear 0.18-μm CMOS power amplifier with deep n-Well structure. 1073-1080 - Ju-Ho Sohn, Jeong-Ho Woo, Min-wuk Lee, Hyejung Kim, Ramchan Woo, Hoi-Jun Yoo:
A 155-mW 50-m vertices/s graphics processor with fixed-point programmable vertex shader for mobile applications. 1081-1091 - Yasuhiko Sasaki, Naoki Kato, Hiroaki Nakaya:
Constant-ratio-coupled multi-grain digital synchronizer with flexible input-output delay selection for versatility in low-power applications. 1092-1099 - Ming-Dou Ker, Shih-Lun Chen, Chia-Sheng Tsai:
Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes. 1100-1107 - Hung-Yu Li, Chia-Cheng Chen, Jinn-Shyan Wang, Chingwei Yeh:
An AND-type match-line scheme for high-performance energy-efficient content addressable memories. 1108-1119 - Daniel L. Kaczman, Manish Shah, Nihal J. Godambe, Mohammed Alam, Homero N. Guimarães, Lu M. Han, Mohammed Rachedine, David L. Cashen, William E. Getka, Charles Dozier, Wayne P. Shepherd, Karl Couglar:
A single-chip tri-band (2100, 1900, 850/800 MHz) WCDMA/HSDPA cellular transceiver. 1122-1132 - Alex W. Hietala:
A quad-band 8PSK/GMSK polar transceiver. 1133-1141