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"A high-resolution CMOS time-to-digital converter utilizing a Vernier delay ..."

Piotr Dudek, Stanislaw Szczepanski, John V. Hatfield (2000)

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DOI: 10.1109/4.823449

access: closed

type: Journal Article

metadata version: 2022-04-08

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Piotr Dudek, Stanislaw Szczepanski, John V. Hatfield:
A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line. IEEE J. Solid State Circuits 35(2): 240-247 (2000)

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