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"A 3.12 pJ/bit, 19-27 Gbps Receiver With 2-Tap DFE Embedded Clock and Data ..."

Zheng-Hao Hong, Yao-Chia Liu, Wei-Zen Chen (2015)

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DOI: 10.1109/JSSC.2015.2475122

access: closed

type: Journal Article

metadata version: 2020-08-30

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  - https://dblp.org/rec/journals/jssc/HongLC15
Zheng-Hao Hong, Yao-Chia Liu, Wei-Zen Chen:
A 3.12 pJ/bit, 19-27 Gbps Receiver With 2-Tap DFE Embedded Clock and Data Recovery. IEEE J. Solid State Circuits 50(11): 2625-2634 (2015)

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