"Layout Synthesis and Loop Parameter Optimization of a Low-Jitter ..."

Wooseok Kim et al. (2014)

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DOI: 10.1109/JSSC.2014.2298455

access: closed

type: Journal Article

metadata version: 2020-08-30

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Wooseok Kim, Jaejin Park, Hojin Park, Deog-Kyoon Jeong:
Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock Generator. IEEE J. Solid State Circuits 49(3): 657-672 (2014)

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