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2020 – today
- 2024
- [j124]Minkyo Shim
, Seungha Roh
, Yunhee Lee
, Jung-Woo Sull
, Deog-Kyoon Jeong
, Kwanseo Park
:
A 50-Gb/s PAM-4 Receiver With Adaptive Phase-Shifting CDR in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 71(8): 3550-3560 (2024) - [j123]Seungha Roh
, Minkyo Shim
, Yoojin Jung
, Deog-Kyoon Jeong
, Kwanseo Park
:
A Low-Jitter Phase Detection Technique With Asymmetric Weights in Multi-Level Baud-Rate CDR. IEEE Trans. Circuits Syst. I Regul. Pap. 71(12): 5861-5872 (2024) - 2023
- [j122]Minkyo Shim
, Woonghee Lee, Yunhee Lee
, Kwanseo Park
, Deog-Kyoon Jeong
:
A 12-Gbps, 0.24-pJ/b/dB PAM-4 Receiver With Dead-Zone Free SS-MMSE PD for CIS Link. IEEE Access 11: 46513-46521 (2023) - [j121]Woosong Jung
, Kwangho Lee, Kwanseo Park
, Haram Ju
, Jinhyung Lee, Deog-Kyoon Jeong
:
A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS. IEEE J. Solid State Circuits 58(5): 1414-1424 (2023) - [j120]Jonghyun Oh
, Young-Ha Hwang
, Jun-Eun Park
, Mingoo Seok
, Deog-Kyoon Jeong
:
An Output-Capacitor-Free Synthesizable Digital LDO Using CMP-Triggered Oscillator and Droop Detector. IEEE J. Solid State Circuits 58(6): 1769-1781 (2023) - [j119]Minkyo Shim
, Kwang-Hoon Lee
, Seungha Roh
, Kwanseo Park
, Deog-Kyoon Jeong
:
A 1.1-pJ/b 8-to-16-Gb/s Receiver With Stochastic CTLE Adaptation. IEEE Trans. Circuits Syst. II Express Briefs 70(2): 381-385 (2023) - [j118]Yunhee Lee
, Minkyo Shim
, Seungha Roh
, Woonghee Lee, Deog-Kyoon Jeong
:
An 80-Gb/s PAM-4 Simultaneous Bidirectional Transceiver With Hybrid Adaptation Scheme. IEEE Trans. Circuits Syst. II Express Briefs 70(8): 2884-2888 (2023) - [j117]Sanghee Lee
, Byungjun Kang
, Woogeun Rhee
, Deog-Kyoon Jeong
:
A 0.061-pJ/b/dB 28-Gb/s Gradient-Based Maximum Eye Tracking CDR With 2-Tap DFE Adaptation in 28-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 70(11): 3998-4002 (2023) - [j116]Kwang-Hoon Lee
, Jung-Hun Park
, Yongjae Lee
, Yeonggeun Song
, Seungha Roh
, Minkyo Shim
, Yoonho Song, Woosong Jung
, Young-Ha Hwang
, Jonghyun Oh
, Woo-Seok Choi
, Deog-Kyoon Jeong
:
A 0.99-pJ/b 10-Gb/s Receiver With Fast Recovery From Sleep Mode Under Voltage Drift. IEEE Trans. Circuits Syst. II Express Briefs 70(11): 4003-4007 (2023) - [j115]Young-Ha Hwang
, Jun Wang, Deog-Kyoon Jeong
, Jun-Eun Park
:
An Area/Power-Efficient ΔΣ Modulator Based on Dynamic-Boost Inverter for Multichannel Sensor Applications. IEEE Trans. Very Large Scale Integr. Syst. 31(9): 1403-1412 (2023) - [c94]Daeho Yun, Minsu Park, Kahyun Kim, Kyungmin Baek, Eonhui Lee, Woo-Seok Choi, Deog-Kyoon Jeong:
A PAM4 Level Mismatch Adjustment Scheme for 48-Gb/s PAM4 Memory Tester Bridge. A-SSCC 2023: 1-3 - [c93]Woosong Jung, Hyojun Kim
, Yeonggeun Song, Kwang-Hoon Lee, Deog-Kyoon Jeong:
A 0.991JS FFT-Based Fast-Locking, 0.82GHz-to-4.lGHz DPLL-Based lnput-Jitter-Filtering Clock Driver with Wide-Range Mode-Switching 8-Shaped LC Oscillator for DRAM Interfaces. CICC 2023: 1-2 - [c92]Woosong Jung, Minkyo Shim, Seungha Roh, Deog-Kyoon Jeong:
A 14-28 Gb/s Reference-less Baud-rate CDR with Integrator-based Stochastic Phase and Frequency Detector. ISCAS 2023: 1-5 - [c91]Kahyun Kim, Daeho Yun, Kyungmin Baek, Woo-Seok Choi, Deog-Kyoon Jeong:
A 48-Gb/s Single-Ended PAM-4 Receiver with Adaptive Nonlinearity Compensation. ISCAS 2023: 1-5 - [c90]Jung-Hun Park, Hyeonseok Lee, Hoyeon Cho, Sanghee Lee, Kwang-Hoon Lee, Han-Gon Ko, Deog-Kyoon Jeong:
A 32Gb/s/pin 0.51 pJ/b Single-Ended Resistor-less Impedance-Matched Transmitter with a T-Coil-Based Edge-Boosting Equalizer in 40nm CMOS. ISSCC 2023: 410-411 - [c89]Jung-Woo Sull, Minkyo Shim, Jung-Hun Park, Sanghee Lee, Deog-Kyoon Jeong:
An 8-GHz Octa-Phase Clock Corrector with Phase and Duty-Cycle Correction in 40-nm CMOS. MWSCAS 2023: 1005-1009 - 2022
- [j114]Kwanseo Park
, Minkyo Shim, Han-Gon Ko
, Borivoje Nikolic
, Deog-Kyoon Jeong
:
Design Techniques for a 6.4-32-Gb/s 0.96-pJ/b Continuous-Rate CDR With Stochastic Frequency-Phase Detector. IEEE J. Solid State Circuits 57(2): 573-585 (2022) - [j113]Hyojun Kim
, Woosong Jung
, Kwandong Kim, Sungwoo Kim
, Woo-Seok Choi
, Deog-Kyoon Jeong
:
A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Loop for Supply Noise Compensation. IEEE J. Solid State Circuits 57(6): 1712-1722 (2022) - [j112]Young-Ha Hwang
, Jonghyun Oh
, Woo-Seok Choi
, Deog-Kyoon Jeong
, Jun-Eun Park
:
A Residue-Current-Locked Hybrid Low-Dropout Regulator Supporting Ultralow Dropout of Sub-50 mV With Fast Settling Time Below 10 ns. IEEE J. Solid State Circuits 57(7): 2236-2249 (2022) - [j111]Haram Ju
, Kwangho Lee
, Kwanseo Park
, Woosong Jung
, Deog-Kyoon Jeong
:
Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector. IEEE J. Solid State Circuits 57(10): 3014-3024 (2022) - [j110]Yeonggeun Song
, Han-Gon Ko
, Changhyun Kim
, Deog-Kyoon Jeong
:
A 1.05-to-3.2 GHz All-Digital PLL for DDR5 Registering Clock Driver With a Self-Biased Supply-Noise-Compensating Ring DCO. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 759-763 (2022) - [j109]Soyeong Shin
, Yongjae Lee
, Jiheon Park
, Jihyo Kang
, Kyunghoon Kim, Dae-Han Kwon, Sangkwon Lee
, Jieun Jang
, Joo-Hwan Cho, Deog-Kyoon Jeong
:
A Clock Distribution Scheme Insensitive to Supply Voltage Drift With Self-Adjustment of Clock Buffer Delay. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 814-818 (2022) - [j108]Jung-Woo Sull
, Soyeong Shin
, Jonghyun Oh
, Kwang-Hoon Lee
, Jihee Kim
, Jung-Hun Park, Deog-Kyoon Jeong
:
An 8-GHz Octa-Phase Error Corrector With Coprime Phase Comparison Scheme in 40-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 874-878 (2022) - [j107]Woonghee Lee
, Minkyo Shim, Yunhee Lee
, Heejin Yang
, Soyeong Shin
, Woo-Seok Choi
, Deog-Kyoon Jeong
:
Area and Power Efficient 10B6Q PAM-4 DC Balance Coder for Automotive Camera Link. IEEE Trans. Circuits Syst. II Express Briefs 69(4): 2056-2060 (2022) - [j106]Moon-Chul Choi
, Sanghee Lee, Seungha Roh, Kwangho Lee
, Jonghyun Oh
, Sungwoo Kim
, Kwandong Kim, Woo-Seok Choi
, Jaeha Kim
, Deog-Kyoon Jeong
:
A 2.5-32 Gb/s Gen 5-PCIe Receiver With Multi-Rate CDR Engine and Hybrid DFE. IEEE Trans. Circuits Syst. II Express Briefs 69(6): 2677-2681 (2022) - [j105]Seungha Roh
, Kwangho Lee
, Minkyo Shim, Moon-Chul Choi
, Deog-Kyoon Jeong
:
A 64-Gb/s PAM-4 Receiver With Transition-Weighted Phase Detector. IEEE Trans. Circuits Syst. II Express Briefs 69(9): 3704-3708 (2022) - [j104]Daeho Yun
, Eonhui Lee, Woosong Jung
, Kahyun Kim, Kyung-Min Beak, Jihee Kim
, Hyun Bae Lee
, Byeongseon Ko, Woo-Seok Choi
, Deog-Kyoon Jeong
:
A 32-Gb/s PAM4-Binary Bridge With Sampler Offset Cancellation for Memory Testing. IEEE Trans. Circuits Syst. II Express Briefs 69(9): 3749-3753 (2022) - [j103]Young-Ha Hwang
, Yoonho Song, Jun-Eun Park
, Deog-Kyoon Jeong
:
A Fully Passive Noise-Shaping SAR ADC Utilizing Last-Bit Majority Voting and Cyclic Dynamic Element Matching Techniques. IEEE Trans. Very Large Scale Integr. Syst. 30(10): 1381-1390 (2022) - [c88]Yeonggeun Song, Kyoungjoon Ha, Han-Gon Ko, Min-Seong Choo, Deog-Kyoon Jeong:
A -247.1 dB FoM, -77.9dBc Reference Spur Ring-Oscillator-Based Injection-Locked Clock Multiplier with Multi-Phase-Based Calibration. ESSCIRC 2022: 249-252 - [c87]Kyungmin Baek, Kahyun Kim, Deog-Kyoon Jeong:
A 5GHz All-Digital PLL with shunt regulating Ring DCO in BOST for DDR5 ATE. ISOCC 2022: 139-140 - [c86]Yoonho Song, Eunseo Kim, Deog-Kyoon Jeong:
Design of Energy Harvesting System with Piezoelectric Device for Onetime-High-Energy Applications. ISOCC 2022: 149-150 - [c85]Hyojun Kim
, Hyeong-Seok Oh, Woosong Jung, Yoonho Song, Jonghyun Oh
, Deog-Kyoon Jeong:
A 100MHz-Reference, 8GHz/16GHz, 177fsrms/223fsrms RO-Based IL-ADPLL Incorporating Reference Octupler with Probability-Based Fast Phase-Error Calibration. ISSCC 2022: 1-3 - [c84]Yunhee Lee
, Woonghee Lee, Minkyo Shim, Soyeong Shin, Woo-Seok Choi, Deog-Kyoon Jeong:
0.41-pJ/b/dB Asymmetric Simultaneous Bidirectional Transceivers With PAM-4 Forward and PAM-2 Back Channels for 5-m Automotive Camera Link. VLSI Technology and Circuits 2022: 30-31 - [c83]Jung-Hun Park, Kwang-Hoon Lee, Yongjae Lee, Jung-Woo Sull, Yoonho Song, Sanghee Lee, Hyeonseok Lee, Hoyeon Cho, Jonghyun Oh, Han-Gon Ko, Deog-Kyoon Jeong:
A 68.7-fJ/b/mm 375-GB/s/mm Single-Ended PAM-4 Interface with Per-Pin Training Sequence for the Next-Generation HBM Controller. VLSI Technology and Circuits 2022: 150-151 - 2021
- [j102]Byungjun Kang
, Gyu-Seob Jeong, Jeongho Hwang
, Kwanseo Park
, Hyungrok Do, Hyojun Kim
, Han-Gon Ko
, Moon-Chul Choi
, Deog-Kyoon Jeong
:
A 10 Gb/s PAM-4 Transmitter With Feed-Forward Implementation of Tomlinson-Harashima Precoding in 28 nm CMOS. IEEE Access 9: 156789-156798 (2021) - [j101]Kwanseo Park
, Kwangho Lee
, Sung-Yong Cho
, Jinhyung Lee, Jeongho Hwang
, Min-Seong Choo
, Deog-Kyoon Jeong
:
A 4-20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS. IEEE J. Solid State Circuits 56(5): 1597-1607 (2021) - [j100]Min-Seong Choo
, Sungwoo Kim, Han-Gon Ko
, Sung-Yong Cho
, Kwanseo Park
, Jinhyung Lee
, Soyeong Shin
, Hankyu Chi, Deog-Kyoon Jeong
:
A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration. IEEE J. Solid State Circuits 56(8): 2525-2538 (2021) - [j99]Chang-Soo Yoon, Han-Gon Ko
, Byung-Jun Kang, Jung-Woo Sull
, Deog-Kyoon Jeong
:
0.76-mW/pF/GHz, 7-GHz Quadrature Resonant Clock With Frequency Tuning Capacitor and Amplitude Control Feedback Loop. IEEE Trans. Circuits Syst. II Express Briefs 68(1): 136-140 (2021) - [j98]Kwangho Lee
, Hyojun Kim
, Woosong Jung, Jinhyung Lee, Haram Ju, Kwanseo Park
, Ook Kim, Deog-Kyoon Jeong
:
An Adaptive Offset Cancellation Scheme and Shared-Summer Adaptive DFE for 0.068 pJ/b/dB 1.62-to-10 Gb/s Low-Power Receiver in 40 nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 68(2): 622-626 (2021) - [c82]Hyungrok Do, Jung-Woo Sull, Seunghyun Lee, Kwangho Lee, Deog-Kyoon Jeong:
A 64 Gb/s 2.09 pJ/b PAM-4 VCSEL Transmitter with Bandwidth Extension Techniques in 40 nm CMOS. A-SSCC 2021: 1-3 - [c81]Haram Ju, Kwangho Lee, Woosong Jung, Deog-Kyoon Jeong:
A 48Gb/s 2.4pJ/b PAM-4 Baud-Rate Digital CDR with Stochastic Phase Detection Technique in 40nm CMOS. A-SSCC 2021: 1-3 - [c80]Kwangho Lee, Woosong Jung, Haram Ju, Jinhyung Lee, Deog-Kyoon Jeong:
A 48 Gb/s PAM4 receiver with Baud-rate phase-detector for multi-level signal modulation in 40 nm CMOS. A-SSCC 2021: 1-3 - [c79]Woonghee Lee, Minkyo Shim, Yunhee Lee
, Heejin Yang
, Han-Gon Ko, Woo-Seok Choi, Deog-Kyoon Jeong:
0.37-pJ/b/dB PAM-4 Transmitter and Adaptive Receiver with Fixed Data and Threshold Levels for 12-m Automotive Camera Link. ESSCIRC 2021: 475-478 - [c78]Seungha Roh, Moon-Chul Choi
, Deog-Kyoon Jeong:
A Maximum Eye Tracking Clock-and-Data Recovery Scheme with Golden Section Search(GSS) Algorithm in 28-nm CMOS. ISOCC 2021: 47-48 - [c77]Minkyo Shim, Woonghee Lee, Yunhee Lee
, Deog-Kyoon Jeong:
A Stochastic Variable Gain Amplifier Adaptation for PAM-4 signaling. ISOCC 2021: 49-50 - [c76]Hong-Seok Choi, Seungha Roh, Sanghee Lee, Jung-Hoon Park, Kwanghoon Lee, Young-Ha Hwang, Deog-Kyoon Jeong:
A 6b 48-GS/s Asynchronous 2b/cycle Time-Interleaved ADC in 28-nm CMOS. ISOCC 2021: 127-128 - [c75]Yunhee Lee
, Woonghee Lee, Minkyo Shim, Deog-Kyoon Jeong:
A Sequential Two-step Algorithm For DC Offset Cancellation of PAM-4 Receiver. ISOCC 2021: 379-380 - [c74]Daeho Yun, Deog-Kyoon Jeong:
Auto-tracking Method with Optimal Reference Voltage for PAM-4 Receiver. ISOCC 2021: 381-382 - 2020
- [j97]Jinhyung Lee
, Kwangho Lee, Hyojun Kim
, Byungmin Kim, Kwanseo Park
, Deog-Kyoon Jeong
:
A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s Video Interface Receiver With Jointly Adaptive CTLE and DFE Using Biased Data-Level Reference. IEEE J. Solid State Circuits 55(8): 2186-2195 (2020) - [j96]Jungmin Yoon
, Hyungrok Do, Daehyun Koh
, Seunghan Oak, Junphyo Lee
, Deog-Kyoon Jeong
:
A Capacitor-Coupled Offset-Canceled Sense Amplifier for DRAMs With Reduced Variation of Decision Threshold Voltage. IEEE J. Solid State Circuits 55(8): 2219-2227 (2020) - [j95]Hyungrok Do, Jeongho Hwang
, Hong-Seok Choi, Deog-Kyoon Jeong
:
A 48 Gb/s PAM-4 Transmitter With 3-Tap FFE Based on Double-Shielded Coplanar Waveguide in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 67-II(9): 1569-1573 (2020) - [j94]Sangyoon Lee
, Han-Gon Ko
, Joo-Hyung Chae
, Soyeong Shin
, Jaekwang Yun, Deog-Kyoon Jeong
, Suhwan Kim
:
A 0.83-pJ/Bit 6.4-Gb/s HBM Base Die Receiver Using a 45° Strobe Phase for Energy-Efficient Skew Compensation. IEEE Trans. Circuits Syst. II Express Briefs 67-II(10): 1735-1739 (2020) - [j93]Soyeong Shin
, Han-Gon Ko
, Chan-Ho Kye, Sang-Yoon Lee
, Jaekwang Yun, Doobock Lee, Hae-Kang Jung, Suhwan Kim
, Deog-Kyoon Jeong
:
A 0.45 pJ/b, 6.4 Gb/s Forwarded-Clock Receiver With DLL-Based Self-Tracking Loop for Unmatched Memory Interfaces. IEEE Trans. Circuits Syst. II Express Briefs 67-II(10): 1814-1818 (2020) - [j92]Jeongho Hwang
, Sang-Hyeok Chu, Gyu-Seob Jeong, Yeojoon Youn, Wooseok Kim, Taeik Kim, Deog-Kyoon Jeong
:
A Programmable On-Chip Reference Oscillator With Slow-Wave Coplanar Waveguide in 14-nm FinFET CMOS. IEEE Trans. Circuits Syst. II Express Briefs 67-II(10): 1834-1838 (2020) - [j91]Jonghyun Oh
, Jun-Eun Park
, Deog-Kyoon Jeong
:
A Highly Synthesizable 0.5-to-1.0-V Digital Low-Dropout Regulator With Adaptive Clocking and Incremental Regulation Scheme. IEEE Trans. Circuits Syst. II Express Briefs 67-II(10): 2174-2178 (2020) - [j90]Chan-Ho Kye, Han-Gon Ko
, Jinhyung Lee
, Deog-Kyoon Jeong
:
A 22-Gb/s 0.95-pJ/b Energy-Efficient Voltage-Mode Transmitter With Time-Based Feedforward Equalization in a 28-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 28(5): 1099-1106 (2020) - [j89]Hye-Yoon Joo
, Jinhyung Lee, Haram Ju, Han-Gon Ko
, Jungmin Yoon
, Byungjun Kang, Deog-Kyoon Jeong
:
A Maximum-Eye-Tracking CDR With Biased Data-Level and Eye Slope Detector for Near-Optimal Timing Adaptation. IEEE Trans. Very Large Scale Integr. Syst. 28(12): 2708-2720 (2020) - [c73]Tae Jun Ham, Sungjun Jung, Seonghak Kim, Young H. Oh, Yeonhong Park, Yoonho Song
, Jung-Hun Park, Sanghee Lee, Kyoung Park, Jae W. Lee, Deog-Kyoon Jeong:
A3: Accelerating Attention Mechanisms in Neural Networks with Approximation. HPCA 2020: 328-341 - [c72]Woosong Jung, Jinhyung Lee, Kwangho Lee, Hyojun Kim, Deog-Kyoon Jeong:
A 8.4Gb/s Low Power Transmitter with 1.66 pJ/b using 40: 1 Serializer for DisplayPort Interface. ISOCC 2020: 41-42 - [c71]Daehyun Koh, Dainel Jeong, Jeongho Hwang, Deog-Kyoon Jeong:
Optical Receiver Front-end for Active Optical Cable in 180 nm CMOS. ISOCC 2020: 43-44 - [c70]Hyojun Kim, Jun-Eun Park, Deog-Kyoon Jeong:
An Area-Efficient Temperature Compensated Sub-Threshold CMOS Voltage Reference. ISOCC 2020: 153-154 - [c69]Jung-Woo Sull, Hyungrok Do, Deog-Kyoon Jeong:
A 112-Gb/s PAM-4 Transmitter with 8: 1 MUX in 28-nm CMOS. ISOCC 2020: 266-267 - [c68]Kwanseo Park, Minkyo Shim, Han-Gon Ko, Deog-Kyoon Jeong:
6.5 A 6.4-to-32Gb/s 0.96pJ/b Referenceless CDR Employing ML-Inspired Stochastic Phase-Frequency Detection Technique in 40nm CMOS. ISSCC 2020: 124-126 - [c67]Han-Gon Ko, Soyeong Shin
, Jonghyun Oh
, Kwanseo Park, Deog-Kyoon Jeong:
6.7 An 8Gb/s/µm FFE-Combined Crosstalk-Cancellation Scheme for HBM on Silicon Interposer with 3D-Staggered Channels. ISSCC 2020: 128-130 - [c66]Minho Choi, Deog-Kyoon Jeong:
18.6 A 92.8%-Peak-Efficiency 60A 48V-to-1V 3-Level Half-Bridge DC-DC Converter with Balanced Voltage on a Flying Capacitor. ISSCC 2020: 296-298 - [c65]Soyeong Shin
, Han-Gon Ko, Sungchun Jang, Dongkyun Kim, Deog-Kyoon Jeong:
22.6 A 0.8-to-2.3GHz Quadrature Error Corrector with Correctable Error Range of 101.6ps Using Minimum Total Delay Tracking and Asynchronous Calibration On-Off Scheme for DRAM Interface. ISSCC 2020: 340-342 - [c64]Jonghyun Oh
, Jun-Eun Park, Young-Ha Hwang
, Deog-Kyoon Jeong:
25.2 A 480mA Output-Capacitor-Free Synthesizable Digital LDO Using CMP- Triggered Oscillator and Droop Detector with 99.99% Current Efficiency, 1.3ns Response Time, and 9.8A/mm2 Current Density. ISSCC 2020: 382-384 - [c63]Jun-Eun Park, Jeongho Hwang
, Jonghyun Oh
, Deog-Kyoon Jeong:
32.4 A 0.4-to-1.2V 0.0057mm2 55fs-Transient-FoM Ring-Amplifier-Based Low-Dropout Regulator with Replica-Based PSR Enhancement. ISSCC 2020: 492-494 - [c62]Moon-Chul Choi
, Han-Gon Ko, Jonghyun Oh, Hye-Yoon Joo, Kwangho Lee, Deog-Kyoon Jeong:
A 0.1-pJ/b/dB 28-Gb/s Maximum-Eye Tracking, Weight-Adjusting MM CDR and Adaptive DFE with Single Shared Error Sampler. VLSI Circuits 2020: 1-2 - [i1]Tae Jun Ham, Sungjun Jung, Seonghak Kim, Young H. Oh, Yeonhong Park, Yoonho Song, Jung-Hun Park, Sanghee Lee, Kyoung Park, Jae W. Lee, Deog-Kyoon Jeong:
A3: Accelerating Attention Mechanisms in Neural Networks with Approximation. CoRR abs/2002.10941 (2020)
2010 – 2019
- 2019
- [j88]Han-Gon Ko
, Woo-Rham Bae
, Gyu-Seob Jeong, Deog-Kyoon Jeong
:
Reference Spur Reduction Techniques for a Phase-Locked Loop. IEEE Access 7: 38035-38043 (2019) - [j87]Jun-Eun Park
, Young-Ha Hwang
, Deog-Kyoon Jeong
:
A 0.5-V Fully Synthesizable SAR ADC for On-Chip Distributed Waveform Monitors. IEEE Access 7: 63686-63697 (2019) - [j86]Jun-Eun Park
, Jiheon Park
, Young-Ha Hwang
, Jonghyun Oh
, Deog-Kyoon Jeong
:
A Noise-Immunity-Enhanced Analog Front-End for $36\times64$ Touch-Screen Controllers With 20- $\text{V}_{\text{PP}}$ Noise Tolerance at 100 kHz. IEEE J. Solid State Circuits 54(5): 1497-1510 (2019) - [j85]Jiheon Park
, Young-Ha Hwang
, Jonghyun Oh
, Yoonho Song
, Jun-Eun Park
, Deog-Kyoon Jeong
:
A Mutual Capacitance Touch Readout IC With 64% Reduced-Power Adiabatic Driving Over Heavily Coupled Touch Screen. IEEE J. Solid State Circuits 54(6): 1694-1704 (2019) - [j84]Min-Seong Choo
, Kwanseo Park
, Han-Gon Ko
, Sung-Yong Cho
, Kwangho Lee, Deog-Kyoon Jeong
:
A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology. IEEE J. Solid State Circuits 54(10): 2812-2822 (2019) - [j83]Gyu-Seob Jeong
, Byungjun Kang, Haram Ju, Kwanseo Park
, Deog-Kyoon Jeong
:
A Modulo-FIR Equalizer for Wireline Communications. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(11): 4278-4286 (2019) - [j82]Moon-Chul Choi
, Deog-Kyoon Jeong
, Sung-Yong Cho, Minkyo Shim, Byungmin Kim, Han-Gon Ko
, Haram Ju, Kwanseo Park
, Hyojun Kim
, Kwandong Kim:
A 2.5-28 Gb/s Multi-Standard Transmitter With Two-Step Time-Multiplexing Driver. IEEE Trans. Circuits Syst. II Express Briefs 66-II(12): 1927-1931 (2019) - [j81]Min-Seong Choo
, Yeonggeun Song
, Sung-Yong Cho
, Han-Gon Ko
, Kwanseo Park
, Deog-Kyoon Jeong
:
A 15-GHz, 17.8-mW, 213-fs Injection-Locked PLL With Maximized Injection Strength Using Adjustment of Phase Domain Response. IEEE Trans. Circuits Syst. II Express Briefs 66-II(12): 1932-1936 (2019) - [c61]Hye-Yoon Joo, Deog-Kyoon Jeong:
A Maximum-Eye-Tracking CDR with Biased Data-Level and Eye Slope Detector for Optimal Timing Adaptation. A-SSCC 2019: 243-244 - [c60]Moon-Chul Choi, Haram Ju, Han-Gon Ko, Deog-Kyoon Jeong:
A Design of Data Path Based on CMOS Logic for a 72-Gb/s PAM-4 Transmitter in 28-nm CMOS. ICEIC 2019: 1-4 - [c59]Jonghyun Oh, Jun-Eun Park
, Deog-Kyoon Jeong:
A $4.7\mu \mathrm{A}$ Quiescent Current Synthesizable Digital Low Dropout Regulator in 28-nm CMOS. ICEIC 2019: 1-2 - [c58]Young-Ha Hwang
, Jonghyun Oh, Jiheon Park, Yoonho Song, Jung-Hun Park, Jun-Eun Park, Deog-Kyoon Jeong:
An Always-On 0.53-to-13.4 mW Power-Scalable Touchscreen Controller for Ultrathin Touchscreen Displays With Current-Mode Filter and Incremental Hybrid ΔΣ ADC. ESSCIRC 2019: 313-316 - [c57]Jiheon Park, Young-Ha Hwang
, Jonghyun Oh
, Yoonho Song, Jun-Eun Park
, Deog-Kyoon Jeong:
A Compact Self-Capacitance Sensing Analog Front-End for a Touch Detection in Low-Power Mode. ISLPED 2019: 1-6 - [c56]Minho Choi, Chan-Ho Kye, Jonghyun Oh
, Min-Seong Choo
, Deog-Kyoon Jeong:
A Synthesizable Digital AOT 4-Phase Buck Voltage Regulator for Digital Systems with 0.0054mm2 Controller and 80ns Recovery Time. ISSCC 2019: 432-434 - [c55]Jeongho Hwang, Hyungrok Do, Hong-Seok Choi, Gyu-Seob Jeong, Daehyun Koh, Sungwoo Kim, Deog-Kyoon Jeong:
56Gb/s PAM-4 VCSEL Transmitter with Quarter-Rate Forwarded Clock using 65nm CMOS Circuits. OFC 2019: 1-3 - [c54]Han-Gon Ko, Soyeong Shin
, Chan-Ho Kye, Sang-Yoon Lee, Jaekwang Yun, Hae-Kang Jung, Doobock Lee, Suhwan Kim, Deog-Kyoon Jeong:
A 370-fJ/b, 0.0056 mm2/DQ, 4.8-Gb/s DQ Receiver for HBM3 with a Baud-Rate Self-Tracking Loop. VLSI Circuits 2019: 94- - [c53]Kwanseo Park, Kwangho Lee, Sung-Yong Cho, Jinhyung Lee, Jeongho Hwang
, Min-Seong Choo
, Deog-Kyoon Jeong:
A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR With Unlimited Frequency Detection Capability in 65nm CMOS. VLSI Circuits 2019: 194- - [c52]Jinhyung Lee, Kwangho Lee, Hyojun Kim
, Byungmin Kim, Kwanseo Park, Deog-Kyoon Jeong:
A 0.1pJ/b/dB 1.62-to-10.8Gb/s Video Interface Receiver with Fully Adaptive Equalization Using Un-Even Data Level. VLSI Circuits 2019: 198- - [c51]Jeongho Hwang
, Hong-Seok Choi, Hyungrok Do, Gyu-Seob Jeong, Daehyun Koh, Kwanseo Park, Sungwoo Kim, Deog-Kyoon Jeong:
A 64Gb/s 2.29pJ/b PAM-4 VCSEL Transmitter With 3-Tap Asymmetric FFE in 65nm CMOS. VLSI Circuits 2019: 268- - 2018
- [j80]Kwanseo Park
, Woo-Rham Bae
, Jinhyung Lee
, Jeongho Hwang
, Deog-Kyoon Jeong
:
A 6.7-11.2 Gb/s, 2.25 pJ/bit, Single-Loop Referenceless CDR With Multi-Phase, Oversampling PFD in 65-nm CMOS. IEEE J. Solid State Circuits 53(10): 2982-2993 (2018) - [j79]Jeongho Hwang
, Gyu-Seob Jeong, Woo-Rham Bae
, Jun-Eun Park
, Chang-Soo Yoon, Jungmin Yoon, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong
:
A 32 Gb/s, 201 mW, MZM/EAM Cascode Push-Pull CML Driver in 65 nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 65-II(4): 436-440 (2018) - [j78]Sung-Yong Cho
, Sungwoo Kim
, Min-Seong Choo
, Han-Gon Ko
, Jinhyung Lee
, Woo-Rham Bae
, Deog-Kyoon Jeong
:
A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(9): 2691-2702 (2018) - [j77]Jinhyung Lee
, Kwanseo Park
, Kwangho Lee, Deog-Kyoon Jeong
:
A 2.44-pJ/b 1.62-10-Gb/s Receiver for Next Generation Video Interface Equalizing 23-dB Loss With Adaptive 2-Tap Data DFE and 1-Tap Edge DFE. IEEE Trans. Circuits Syst. II Express Briefs 65-II(10): 1295-1299 (2018) - [j76]Gyu-Seob Jeong
, Jeongho Hwang
, Hong-Seok Choi, Hyungrok Do, Daehyun Koh, Daeyoung Yun, Jinhyung Lee
, Kwanseo Park
, Han-Gon Ko
, Kwangho Lee, Jiho Joo
, Gyungock Kim, Deog-Kyoon Jeong
:
25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections. IEEE Trans. Circuits Syst. II Express Briefs 65-II(10): 1395-1399 (2018) - [j75]Young-Ha Hwang
, Jun-Eun Park
, Yoonho Song, Deog-Kyoon Jeong
:
A 20 k-to-100kS/s Sub-µW 9.5b-ENOB Asynchronous SAR ADC for Energy-Harvesting Body Sensor Node SoCs in 0.18-µm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 65-II(12): 1814-1818 (2018) - [j74]Min-Seong Choo
, Han-Gon Ko
, Sung-Yong Cho
, Kwangho Lee, Deog-Kyoon Jeong
:
An Optimum Injection-Timing Tracking Loop for 5-GHz, 1.13-mW/GHz RO-Based Injection-Locked PLL With 152-fs Integrated Jitter. IEEE Trans. Circuits Syst. II Express Briefs 65-II(12): 1819-1823 (2018) - [j73]Hong-Seok Choi, Jeongho Hwang
, Gyu-Seob Jeong
, Gyungock Kim, Deog-Kyoon Jeong
:
A 35-Gb/s 0.65-pJ/b Asymmetric Push-Pull Inverter-Based VCSEL Driver With Series Inductive Peaking in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 65-II(12): 1824-1828 (2018) - [j72]Mino Kim, Joo-Hyung Chae
, Sungphil Choi
, Gi-Moon Hong, Hyeongjun Ko, Deog-Kyoon Jeong
, Suhwan Kim
:
A 4266 Mb/s/pin LPDDR4 Interface With An Asynchronous Feedback CTLE and An Adaptive 3-Step Eye Detection Algorithm for Memory Controller. IEEE Trans. Circuits Syst. II Express Briefs 65-II(12): 1894-1898 (2018) - [j71]Woo-Rham Bae
, Haram Ju, Kwanseo Park
, Jaeduk Han, Deog-Kyoon Jeong
:
A Supply-Scalable-Serializing Transmitter With Controllable Output Swing and Equalization for Next-Generation Standards. IEEE Trans. Ind. Electron. 65(7): 5979-5989 (2018) - [c50]Min-Seong Choo
, Han-Gon Ko, Sung-Yong Cho, Kwangho Lee, Deog-Kyoon Jeong:
A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate All-Digital Injection-Locked Clock and Data Recovery with Maximum Timing-Margin Tracking Loop. A-SSCC 2018: 73-76 - [c49]Young-Ha Hwang
, Yoonho Song
, Jun-Eun Park
, Deog-Kyoon Jeong:
A 0.6-to-1V 10k-to-100kHz BW 11.7b-ENOB Noise-Shaping SAR ADC for IoT sensor applications in 28-nm CMOS. A-SSCC 2018: 247-248 - [c48]