"An experimental 295 MHz CMOS 4K⨉256 SRAM using bidirectional ..."

Natsuki Kushiyama et al. (1995)

> Home

Details and statistics

DOI: 10.1109/4.475718

access: closed

type: Journal Article

metadata version: 2023-05-09

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/KushiyamaTCLPMLCC95
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/KushiyamaTCLPMLCC95
Natsuki Kushiyama, Charles Tan, Richard Clark, Jane Lin, Fred Perner, Lisa Martin, Mark Leonard, Gene Coussens, Kit Cham:
An experimental 295 MHz CMOS 4K⨉256 SRAM using bidirectional read/write shared sense amps and self-timed pulsed word-line drivers. IEEE J. Solid State Circuits 30(11): 1286-1290 (1995)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.