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ORCIDIEEE Journal of Solid-State Circuits, Volume 30
Volume 30, Number 1, January 1995
- Robert A. Hawley, Thu-ji Lin, Henry Samueli:
A 300 MHz digital double-sideband to single-sideband converter in 1 μm CMOS. 4-10 - Nader Mirfakhraei:
Design of a CMOS buffered switch for a Gigabit ATM switching network. 11-18 - Kiyoshi Ishii, Haruhiko Ichino, Minoru Togashi, Yoshiji Kobayashi, Chikara Yamaguchi:
Very-high-speed Si bipolar static frequency dividers with new T-type flip-flops. 19-24 - Toshiaki Eirihata, Sang H. Dhong, Lewis M. Terman, Toshio Sunaga, Yoischi Taira:
A variable precharge voltage sensing. 25-28 - Richard F. Hobson, Michael W. Fraser:
An efficient maximum-redundancy radix-8 SRT division and square-root method. 29-38 - Clemenz L. Portmann, Teresa H. Y. Meng:
Metastability in CMOS library elements in reduced supply and technology scaled applications. 39-46 - Sherif H. K. Embabi, Abdellatif Bellaouar, Kazi Islam:
A bootstrapped bipolar CMOS (B2CMOS) Gate for low-voltage applications. 47-53 - Yutaka Harada:
Delay components of a current mode logic circuit and their current dependency. 54-60 - Nobuo Kotera, Kiichi Yamashita, Keiichi Kitamura, Yasushi Hatta:
Constant-current circuit-biasing technology for GaAs FET IC. 61-64 - Robert G. Meyer:
Low-power monolithic RF peak detector analysis. 65-67 - Tien-Yu Wu, Ching-Tsing Jih, Jueh-Chi Chen, Chung-Yu Wu:
A low glitch 10-bit 75-MHz CMOS video D/A converter. 68-72 - James B. Kuo, K. W. Su, J. H. Lou, S. S. Chen, C. S. Chiang:
A 1.5 V full-swing BiCMOS dynamic logic gate circuit suitable for VLSI using low-voltage BiCMOS technology. 73-75 - Chung-Yu Wu, Chih-Cheng Chen, Jyh-Jer Cho:
Precise CMOS current sample/hold circuits using differential clock feedthrough attenuation techniques. 76-80
Volume 30, Number 2, February 1995
- Keiko Makie-Fukuda, Takafumi Kikuchi, Tatsuji Matsuura, Masao Hotta:
Measurement of digital noise in mixed-signal integrated circuits. 87-92 - Navid Foroudi, Tadeusz Kwasniewski:
CMOS high-speed dual-modulus frequency divider for RF frequency synthesis. 93-100 - Behzad Razavi, Kwing F. Lee, Ran H. Yan:
Design of high-speed, low-power frequency dividers and phase-locked loops in deep submicron CMOS. 101-109 - Suharli Tedja, Jan Van der Speigel, Hugh H. Williams:
A CMOS low-noise and low-power charge sampling integrated circuit for capacitive detector/sensor interfaces. 110-119 - Ivars G. Finvers, James W. Haslett, Fred N. Trofimenkoff:
A high temperature precision amplifier. 120-128 - Zhihao Lao, Ulrich Langmann, Jens N. Albers, Erwin Schlag, Detlef Clawin:
A 12 Gb/s Si bipolar 4:1-multiplexer IC for SDH systems. 129-132 - Jerry Jex, Charles Dike:
A fast resolving BiNMOS synchronizer for parallel processor interconnect. 133-139 - V. Chandramouli, Nick Michell, Kent F. Smith:
A new, precharged, low-power logic family for GaAs circuits. 140-143 - John G. Kenney, Giri Rangan, Karthik Ramamurthy, Gabor C. Temes:
An enhanced slew rate source follower. 144-146 - Ashraf A. Osman, Mohamed A. Osman, Numan S. Dogan, Mohamed A. Imam:
An extended Tanh law MOSFET model for high temperature circuit simulation. 147-150 - Brian S. Cherkauer, Eby G. Friedman:
Design of tapered buffers with local interconnect capacitance. 151-155 - J. Francisco Duque-Carrillo
, Raquel Pérez-Aloe, José M. Valverde:
Biasing circuit for high input swing operational amplifiers. 156-159
Volume 30, Number 3, March 1995
- Thomas Byunghak Cho, Paul R. Gray:
A 10 b, 20 Msample/s, 35 mW pipeline A/D converter. 166-172 - Katsufumi Nakamura, Masso Hotta, L. Richard Carley, David J. Allstot:
An 85 mW, 10 b, 40 Msample/s CMOS parallel-pipelined ADC. 173-183 - Frank W. Singor, W. Martin Snelgrove:
Switched-capacitor bandpass delta-sigma A/D modulation at 10.7 MHz. 184-192 - Loke Kun Tan, Henry Samueli:
A 200 MHz quadrature digital synthesizer/mixer in 0.8 μm CMOS. 193-200 - Prabir C. Maulik, Nicholas van Bavel, Keith S. Albright, Xue-Mei Gong:
An analog/digital interface for cellular telephony. 201-209 - L. Ingmar Andersson, Björn G. R. Rudberg, P. Thomas Lewin, Michael D. Reed, Sylvia M. Planer, Sam L. Sundaram:
Silicon bipolar chipset for SONET/SDH 10 Gb/s fiber-optic communication links. 210-218 - Erik De Man, Michael Schulz, Richard Schmidmaier, Matthias Schöbinger, Tobias G. Noll:
Architecture and circuit design of a 6-GOPS signal processor for QAM demodulator applications. 219-227 - Caesar S. H. Wong, Jacques C. Rudell, Gregory T. Uehara, Paul R. Gray:
A 50 MHz eight-tap adaptive equalizer for partial-response channels. 228-234 - Peter R. Kinget, Michel S. J. Steyaert:
A programmable analog cellular neural network CMOS chip for high speed image processing. 235-243 - Rob B. Yates, Neil A. Thacker, Stephen J. Evans, Simon N. Walker, Peter A. Ivey:
An array processor for general purpose digital image compression. 244-250 - Norio Ohkubo, Makoto Suzuki, Toshinobu Shinbo, Toshiaki Yamanaka, Akihiro Shimizu, Katsuro Sasaki, Yoshinobu Nakagome:
A 4.4 ns CMOS 54⨉54-b multiplier using pass-transistor multiplexer. 251-257 - Luca Benini, Giovanni De Micheli:
State assignment for low power dissipation. 258-268 - Sujoy Mitra, Rob A. Rutenbar, L. Richard Carley, David J. Allstot:
Substrate-aware mixed-signal macrocell placement in WRIGHT. 269-278 - Martin O'Leary, Colin Lyden:
Parametric yield prediction of complex, mixed-signal IC's. 279-285 - Steven M. Domer, Samuel A. Foertsch, Glenn D. Raskin:
Model for yield and manufacturing prediction on VLSI designs for advanced technologies, mixed circuitry, and memories. 286-294 - Shobha R. Mallarapu, Albert J. Hoffman:
IDDQ testing on a custom automotive IC. 295-299 - E. Bidet, Damien Castelain, C. Joanblanq, Patrice Senn:
A fast single-chip implementation of 8192 complex point FFT. 300-305 - Ulrich Kaiser, Wolfgang Steinhagen:
A low-power transponder IC for high-performance identification systems. 306-310 - Alex G. Dickinson, John S. Denker:
Adiabatic dynamic logic. 311-315 - Koji Nii, Hideshi Maeno, Tokuya Osawa, Shuhei Iwade, Shinpei Kayano, Hiroshi Shibata:
A novel memory cell for multiport RAM on 0.5 μm CMOS Sea-of-Gates. 316-320 - Balsha R. Stanisic, Rob A. Rutenbar, L. Richard Carley:
Addressing noise decoupling in mixed-signal IC's: power distribution design and cell customization. 321-326 - Piet Wambacq, Francisco V. Fernández, Georges G. E. Gielen, Willy Sansen, Ángel Rodríguez-Vázquez:
Efficient symbolic computation of approximated small-signal characteristics of analog integrated circuits. 327-330
Volume 30, Number 4, April 1995
- Takeo Koinuma, Noriharu Miyaho:
ATM in B-ISDN communication systems and VLSI realization. 341-347 - Shigeki Hino, Minoru Togashi, Kimiyoshi Yamasaki:
Asynchronous transfer mode switching LSI chips with 10-Gb/s serial I/O ports. 348-352 - Kyeongho Lee, Sungjoon Kim, Gijung Ahn, Deog-Kyoon Jeong:
A CMOS serial link for fully duplexed data communication. 353-364 - Frederick P. Herrmann, Charles G. Sodini:
A 256-element associative parallel processor. 365-370 - Maurice P. Marks:
Future directions in microprocessor technology. 371-374 - Masato Motomura, Toshiaki Inoue, Hachiro Yamada, Akihiko Konagaya:
Cache-processor coupling: a fast and wide on-chip data cache design. 375-382 - Jose Alvarez, Hector Sanchez, Gianfranco Gerosa, Roger Countryman:
A wide-bandwidth low-voltage PLL for PowerPC microprocessors. 383-391 - Robert J. Landers, Shivaling S. Mahant-Shetti, Carl Lemonds:
A multiplexer-based architecture for high-density, low-power gate arrays. 392-396 - Mitsuru Hiraki, Hirotsugu Kojima, Hitoshi Misawa, Takashi Akazawa, Yuji Hatano:
Data-dependent logic swing internal bus architecture for ultralow-power LSI's. 397-402 - Paul J. Hurst, Bret C. Rothenberg:
A programmable clock generator that uses noise shaping and its application in switched-capacitor filters. 403-411 - Jim Dunning, Gerald Garcia, Jim Lundberg, Ed Nuckolls:
An all-digital phase-locked loop with 50-cycle lock time suitable for high-performance microprocessors. 412-422 - Hiroyuki Yamauchi, Hironori Akamatsu, Tsutomu Fujita:
An asymptotically zero power charge-recycling bus architecture for battery-operated ultrahigh data rate ULSI's. 423-431 - Hirotsugu Kojima, Satoshi Tanaka, Katsuro Sasaki:
Half-swing clocking scheme for 75% power saving in clocking circuitry. 432-435 - Toshio Sudo:
Present and future directions for multichip module technologies. 436-442 - Tzi-Hsiung Shu, Bang-Sup Song, Kantilal Bacrania:
A 13-b 10-Msample/s ADC digitally calibrated with oversampling delta-sigma converter. 443-452 - Feng Chen, Bosco H. Leung:
A high resolution multibit sigma-delta modulator with individual level averaging. 453-460 - Krhishnaswamy Nagaraj, Stephen H. Lewis, Robert W. Walden, Glen E. Offord, Reza S. Shariatdoust, Jyoti A. Sabnis, Robert O. Peruzzi, Jeffrey R. Barner, Joseph Plany, Robert P. Mento, Vafa A. Rakshani, Richard W. Hull:
A median peak detecting analog signal processor for hard disk drive servo. 461-470 - Tsukasa Ooishi, Yuichiro Komiya, Kei Hamade, Mho Asakura, Kenichi Yasuda, Kiyohiro Furutani, Hideto Hidaka, Hiroshi Miyamoto, Hideyuki Ozaki:
An automatic temperature compensation of internal sense ground for subquarter micron DRAM's. 471-479 - Koichiro Ishibashi, Koichi Takasugi, Kunihiro Komiyaji, Hiroshi Toyoshima, Toshiaki Yamanaka, Akira Fukami, Naotaka Hashimoto, Nagatoshi Ohki, Akihiro Shimizu, Takashi Hashimoto, Takahiro Nagano, Takashi Nishida:
A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers. 480-486 - Suguru Tachibana, Hisayuki Higuchi, Koichi Takasugi, Katsuro Sasaki, Toshiaki Yamanaka, Yoshinobu Nakagome:
A 2.6-ns wave-pipelined CMOS SRAM with dual-sensing-latch circuits. 487-490 - Hiroalu Nambu, Kazuo Kanetani, Youji Idei, Tom Masuda, Keiichi Higeta, Masayuki Ohayashi, Masami Usami, Kunihiko Yamaguchi, Toshiyuki Kikuchi, Takahide Ikeda, Kenichi Ohhata, Takeshi Kusunoki, Noriyuki Homma:
A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM. 491-499 - Kevin J. O'Connor:
A source sensing technique applied to SRAM cells. 500-511
Volume 30, Number 5, May 1995
- Won-Chul Song, Hae-Wook Choi, Sung-Ung Kwak, Bang-Sup Song:
A 10-b 20-Msample/s low-power CMOS ADC. 514-521 - Chung-Yu Wu, Chih-Cheng Chen, Jyh-Jer Cho:
A CMOS transistor-only 8-b 4.5-Ms/s pipelined analog-to-digital converter using fully-differential current-mode circuit techniques. 522-532 - Steven L. Garverick, Lany Skrenes, Richard D. Baertsch:
A 32-channel charge readout IC for programmable, nonlinear quantization of multichannel detector data. 533-541 - Richard Coggins, Marwan A. Jabri, Barry Flower, Stephen Pickard:
A hybrid analog and digital VLSI neural network for intracardiac morphology classification. 542-550 - Michael Schröter, Hans-Martin Rein:
Investigation of very fast and high-current transients in digital bipolar IC's using both a new compact model and a device simulator. 551-562 - Richard X. Gu, Mohamed I. Elmasry:
Novel high speed circuit structures for BiCMOS environment. 563-570 - Robert J. Evans, Paul D. Franzon:
Energy consumption modeling and optimization for SRAM's. 571-579 - Fleming Hoeg, Stephen I. Long, Uddalak Bhattacharya:
Design and performance of multistage GaAs dynamic logic. 580-585 - Khong-Meng Tham, Krishnaswamy Nagaraj:
A low supply voltage high PSRR voltage reference in CMOS process. 586-590 - Richard J. Reay, Gregory T. A. Kovacs:
An unconditionally stable two-stage CMOS amplifier. 591-594 - Srinagesh Satyanarayana, Ken Suyama:
Resistive interpolation biasing: a technique for compensating linear variation in an array of MOS current sources. 595-598 - Nianxiong Tan, Sven Eriksson:
A low-voltage switched-current delta-sigma modulator. 599-603 - Ming-Jer Chen, Yen-Bin Gu, Terry Wu, Po-Chin Hsu, Tsung-Hann Liu:
Weak inversion charge injection in analog MOS switches. 604-606 - Wilhelmus A. M. Van Noije, W. T. Liu, João Navarro Jr.:
Precise final state determination of mismatched CMOS latches. 607-611 - Rainer H. Derksen:
Novel switched current source for increasing output signal edge steepness of current switches without generating large overshoot. 612-615 - Changsik Yoo, Min-Kyu Kim, Wonchan Kim:
A static power saving TTL-to-CMOS input buffer. 616-620
Volume 30, Number 6, June 1995
- Yasunobu Nakase, Hiroaki Suzuki, Hiroshi Makino, Hirofumi Shinohara, Koichiro Mashiko:
A BiCMOS wired-OR logic. 622-628 - Abdellatif Bellaouar, Mohamed I. Elmasry, Sherif H. K. Embabi:
Bootstrapped full-swing BiCMOS/BiNMOS logic circuits for 1.2-3.3 V supply voltage regime. 629-636 - Tohru Kimura, Kazuyuki Nakamura, Yoshiharu Aimoto, Takashi Manabe, Nobuyuki Yamashita, Yoshihiro Fujita, Shin'ichiro Okazaki, Masakazu Yamashina:
Design of 1.28-GB/s high bandwidth 2-Mb SRAM for integrated memory array processor applications. 637-643 - Vei-Han Chan, James E. Chung:
The impact of NMOSFET hot-carrier degradation on CMOS analog subcircuit performance. 644-649 - Maurizio Zuffada, Roberto Alini, Paolo Colletti, Marco Demicheli, Marco Gregori, David Moloney, Salvatore Portaluri, Fabrizio Sacchi, Sadik O. Arf, Vincent Condito, Rinaldo Castello:
A single-chip 9-32 mb/s read/write channel for disk-drive applications. 650-659 - Alessandro Mortara, Eric A. Vittoz, Philippe Venier:
A communication scheme for analog VLSI perceptive systems. 660-669 - C. Andrew Lish:
A class A/B floating buffer BiCMOS power op-amp. 670-676 - Tongtod Vanisri, Chris Toumazou:
Integrated high frequency low-noise current-mode optical transimpedance preamplifiers: theory and practice. 677-685 - R. Pereira, Juan A. Michell, José M. Solana:
Fully pipelined TSPC barrel shifter for high-speed applications. 686-690 - Khaled M. Sharaf, Mohamed I. Elmasry:
Active-pull-down nonthreshold logic BiCMOS circuits for high-speed low-power applications. 691-695 - Abdellatif Bellaouar, Issam S. Abu-Khater, Mohamed I. Elmasry:
Low-power CMOS/BiCMOS drivers and receivers for on-chip interconnects. 696-700 - C. T. Chuang, B. Wu, C. J. Anderson:
High-speed low-power cross-coupled active-pull-down ECL circuit. 701-705 - Massimo Lanzoni, Bruno Riccò:
Experimental characterization of circuits for controlled programming of floating-gate MOSFET's. 706-709 - W. Timothy Holman, J. Alvin Connelly:
A compact low noise operational amplifier for a 1.2 μm digital CMOS technology. 710-714 - Nuno Paulino, José E. Franca, F. P. Martins:
Programmable CMOS switched-capacitor biquad using quasi-passive algorithmic DAC's. 715-719
Volume 30, Number 7, July 1995
- Behzad Razavi:
Design of a 100-MHz 10-mW 3-V sample-and-hold amplifier in digital bipolar technology. 724-730 - Zhong Yuan Chang, Didier Haspeslagh:
A CMOS differential buffer amplifier with accurate gain and clipping control. 731-735 - Jan Crols, Michel S. J. Steyaert:
A 1.5 GHz highly linear CMOS downconversion mixer. 736-742 - Michel S. J. Steyaert, Wim Dehaene, Jan Craninckx, Mairtin Walsh, Peter Real:
A CMOS rectifier-integrator for amplitude detection in hard disk servo loops. 743-751 - Gerhard Nebel, Ulrich Kleine, Hans-Jörg Pfleiderer:
Symbolic pole/zero calculation using SANTAFE. 752-761 - Fernando Medeiro, Belén Pérez-Verdú, Ángel Rodríguez-Vázquez, José L. Huertas:
A vertically integrated tool for automated design of ΣΔ modulators. 762-772 - Koen Lampaert, Georges G. E. Gielen, Willy M. C. Sansen:
A performance-driven placement tool for analog integrated circuits. 773-780 - Martin Rau, Hans-Jörg Pfleiderer:
An ECL to CMOS level converter with complementary bipolar output stage. 781-787 - Geert A. De Veirman, Shunsaku Ueda, Jackie Cheng, Stephen Tam, Kiyoshi Fukahori, Masafumi Kurisu, Eiji Shinozaki:
A 3.0 V 40 Mb/s hard disk drive read channel IC. 788-799 - Andrea Simoni, Guido Torelli, Franco Maloberti, Alvise Sartori, Sofoklis E. Plevridis, Alexios N. Birbas:
A single-chip optical sensor with analog memory for motion detection. 800-806 - Reinhard Kauert, Wolfram Budde, Andreas Kalz:
A monolithic field segment photo sensor system. 807-811 - Olaf J. Joeressen, Heinrich Meyr:
A 40 Mb/s soft-output Viterbi decoder. 812-818 - Jiri Nedved, Jozef Vanneuville, Donne Gevaert, Jan Sevenhans:
A transistor-only switched current sigma-delta A/D converter for a CMOS speech CODEC. 819-822 - Marcel J. M. Pelgrom, Eise Carel Dijkmans:
A 3/5 V compatible I/O buffer. 823-825 - Horst Schleifer, Thomas v. d. Ropp, Kurt Hoffmann, Werner Reczek:
Design concept for radiation hardening of low power and low voltage dynamic memories. 826-829 - T. Juhnke, Heinrich Klar:
Calculation of the soft error rate of submicron CMOS logic circuits. 830-834 - Antonio J. Acosta, Manuel Valencia, Angel Barriga, Manuel J. Bellido, José L. Huertas:
SODS: a new CMOS differential-type structure. 835-838 - O. Salomon, Jorg-Michael Green, Heinrich Klar:
General algorithms for a simplified addition of 2's complement numbers. 839-844
Volume 30, Number 8, August 1995
- Shin'ichiro Mutoh, Takakuni Douseki, Yasuyuki Matsuya, Takahko Aoki, Satoshi Shigematsu, Junzo Yamada:
1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS. 847-854 - Sankaran M. Menon, Yashwant K. Malaiya, Anura P. Jayasumana, Rochit Rajsuman:
Testable design of BiCMOS circuits for stuck-open fault detection using single patterns. 855-863 - Santanu Dutta, Shivaling S. Mahant-Shetti, Stephen L. Lusky:
A comprehensive delay model for CMOS inverters. 864-871 - Edwin X. Li, Norman Scheinberg, Daniel Stofman, William Tompkins:
An independently matched parameter SPICE model for GaAs MESFET's. 872-880