"Dynamically shift-switched dataline redundancy suitable for DRAM macro ..."

Toshimasa Namekawa et al. (2000)

> Home

Details and statistics

DOI: 10.1109/4.841497

access: closed

type: Journal Article

metadata version: 2022-04-08

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/NamekawaMFHWBTS00
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/NamekawaMFHWBTS00
Toshimasa Namekawa, Shinji Miyano, Ryo Fukuda, Ryo Haga, Osamu Wada, Hironori Banba, Satoru Takeda, Kazuhiro Suda, Kenichiro Mimoto, Satoshi Yamaguchi, Tsutomu Ohkubo, Hiroshi Takato, Kenji Numata:
Dynamically shift-switched dataline redundancy suitable for DRAM macro with wide data bus. IEEE J. Solid State Circuits 35(5): 705-712 (2000)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.