"A 9-ns HIT-delay 32-kbyte cache macro for high-speed RISC."

Kazutaka Nogami et al. (1990)

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DOI: 10.1109/4.50291

access: closed

type: Journal Article

metadata version: 2025-01-23

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Kazutaka Nogami, Takayasu Sakurai, Kazuhiro Sawada, Kenji Sakaue, Yuichi Miyazawa, Shinichi Tanaka, Ypocjo Hiruta, Katsuto Katoh, Toshinari Takayanagi, Tsukasa Shirotori, Yasuo Itoh, Masanori Uchida, Tetsuya Iizuka:
A 9-ns HIT-delay 32-kbyte cache macro for high-speed RISC. IEEE J. Solid State Circuits 25(1): 100-108 (1990)

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