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"A 12.5-Gb/s Parallel Phase Detection Clock and Data Recovery Circuit in ..."

Yusuke Ohtomo, Kazuyoshi Nishimura, Masafumi Nogawa (2006)

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DOI: 10.1109/JSSC.2006.880617

access: closed

type: Journal Article

metadata version: 2021-10-15

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  - https://dblp.org/rec/journals/jssc/OhtomoNN06
Yusuke Ohtomo, Kazuyoshi Nishimura, Masafumi Nogawa:
A 12.5-Gb/s Parallel Phase Detection Clock and Data Recovery Circuit in 0.13-$muhbox m$CMOS. IEEE J. Solid State Circuits 41(9): 2052-2057 (2006)

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