"A 200-MFLOPS 100-MHz 64-b BiCMOS vector-pipelined processor (VPP) ULSI."

Fuyuki Okamoto et al. (1991)

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DOI: 10.1109/4.104180

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type: Journal Article

metadata version: 2025-02-26

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Fuyuki Okamoto, Yasuhiko Hagihara, Chie Ohkubo, Naoki Nishi, Hachiro Yamada, Tadayoshi Enomoto:
A 200-MFLOPS 100-MHz 64-b BiCMOS vector-pipelined processor (VPP) ULSI. IEEE J. Solid State Circuits 26(12): 1885-1893 (1991)

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