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"A 1.25-GS/s 7-b SAR ADC With 36.4-dB SNDR at 5 GHz Using ..."

Athanasios Ramkaj et al. (2018)

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DOI: 10.1109/JSSC.2018.2822823

access: closed

type: Journal Article

metadata version: 2020-08-30

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Athanasios Ramkaj, Maarten Strackx, Michiel S. J. Steyaert, Filip Tavernier:
A 1.25-GS/s 7-b SAR ADC With 36.4-dB SNDR at 5 GHz Using Switch-Bootstrapping, USPC DAC and Triple-Tail Comparator in 28-nm CMOS. IEEE J. Solid State Circuits 53(7): 1889-1901 (2018)

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