"A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die ..."

Yesin Ryu et al. (2023)

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DOI: 10.1109/JSSC.2022.3232096

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type: Journal Article

metadata version: 2025-04-29

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Yesin Ryu, Sung-Gi Ahn, Jaehoon Lee, Jaewon Park, Yong-Ki Kim, Hyochang Kim, Yeong Geol Song, Han-Won Cho, Sunghye Cho, Seung Ho Song, Haesuk Lee, Useung Shin, Jonghyun Ahn, Je-Min Ryu, Sukhan Lee, Kyounghwan Lim, Jungyu Lee, Jeong Hoan Park, Jae-Seung Jeong, Sunghwan Jo, Dajung Cho, Sooyoung Kim, Minsu Lee, Hyunho Kim, Minhwan Kim, Jae San Kim, Jinah Kim, Hyun Gil Kang, Myung-Kyu Lee, Sung-Rae Kim, Young-Cheon Kwon, Young-Yong Byun, Kijun Lee, Sangkil Park, Jaeyoun Youn, Myeong-O. Kim, Kyomin Sohn, SangJoon Hwang, JooYoung Lee:
A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features. IEEE J. Solid State Circuits 58(4): 1051-1061 (2023)

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