"A 1.3-cycle lock time, non-PLL/DLL clock multiplier based on direct clock ..."

Takanori Saeki et al. (2000)

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DOI: 10.1109/4.881203

access: closed

type: Journal Article

metadata version: 2022-04-08

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Takanori Saeki, Masafumi Mitsuishi, Hiroaki Iwaki, Mitsuaki Tagishi:
A 1.3-cycle lock time, non-PLL/DLL clock multiplier based on direct clock cycle interpolation for "clock on demand". IEEE J. Solid State Circuits 35(11): 1581-1590 (2000)

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