"A 2× Time-Interleaved 4-GS/s 14-Bit DAC With On-Chip Calibration of ..."

Zhou Shu et al. (2025)

> Home

Details and statistics

DOI: 10.1109/JSSC.2025.3563976

access: closed

type: Journal Article

metadata version: 2025-11-18

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/ShuZLZGHGZ25
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/ShuZLZGHGZ25
Zhou Shu, Jiandong Zang, Qinghao Liu, Tantan Zhang, Yuan Gao, Chun-Huat Heng, Yongxin Guo, Zhangming Zhu:
A 2× Time-Interleaved 4-GS/s 14-Bit DAC With On-Chip Calibration of Interleaving Nonlinearities. IEEE J. Solid State Circuits 60(11): 4073-4087 (2025)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.