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ORCID"A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction ..."
Wanghua Wu et al. (2021)
- Wanghua Wu
, Chih-Wei Yao, Chengkai Guo, Pei-Yuan Chiang, Lei Chen, Pak-Kim Lau, Zhanjun Bai, Sang Won Son, Thomas Byunghak Cho:
A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO. IEEE J. Solid State Circuits 56(12): 3756-3767 (2021)
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