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2020 – today
- 2022
[j8]Wanghua Wu, Hiroyuki Ito, Jens Anders, Ahmed M. A. Ali
, Gaël Pillonnet:
Guest Editorial Introduction to the Special Issue on the 2022 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits 57(12): 3509-3513 (2022)- [c10]Ashutosh Verma, Venumadhav Bhagavatula, Amitoj Singh, Wanghua Wu, Hariharan Nagarajan, Pak-Kim Lau, Xiaohua Yu, Omar Elsayed, Ajaypat Jain, Anirban Sarkar, Fan Zhang, Che-Chun Kuo, Patrick McElwee, Pei-Yuan Chiang, Chengkai Guo, Zhanjun Bai, Tienyu Chang, Abishek Mann, Andreas Rydin, Xingliang Zhao, Jeiyoung Lee, Daeyoung Yoon, Chih-Wei Yao, Siuchuang-Ivan Lu, Sang Won Son, Thomas Byunghak Cho:
A 16-Channel, 28/39GHz Dual-Polarized 5G FR2 Phased-Array Transceiver IC with a Quad-Stream IF Transceiver Supporting Non-Contiguous Carrier Aggregation up to 1.6GHz BW. ISSCC 2022: 1-3 - 2021
- [j7]Wanghua Wu, Chih-Wei Yao, Chengkai Guo, Pei-Yuan Chiang, Lei Chen, Pak-Kim Lau, Zhanjun Bai, Sang Won Son, Thomas Byunghak Cho:
A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO. IEEE J. Solid State Circuits 56(12): 3756-3767 (2021) - [c9]Wei Deng, Jaehyouk Choi, Wanghua Wu:
Session 32 Overview: Frequency Synthesizers Rf Subcommittee. ISSCC 2021: 440-441 - [c8]Wanghua Wu, Chih-Wei Yao, Chengkai Guo, Pei-Yuan Chiang, Pak-Kim Lau, Lei Chen, Sang Won Son, Thomas Byunghak Cho:
32.2 A 14nm Analog Sampling Fractional-N PLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 80fs Integrated Jitter and 93fs at Near-Integer Channels. ISSCC 2021: 444-446
2010 – 2019
- 2019
- [j6]Wanghua Wu, Chih-Wei Yao, Kunal Godbole, Ronghua Ni, Pei-Yuan Chiang, Yongping Han, Yongrong Zuo, Ashutosh Verma, Ivan Siu-Chuang Lu, Sang Won Son, Thomas Byunghak Cho:
A 28-nm 75-fsrms Analog Fractional- $N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction. IEEE J. Solid State Circuits 54(5): 1254-1265 (2019) - 2017
- [j5]Chih-Wei Yao, Ronghua Ni, Chung Lau, Wanghua Wu, Kunal Godbole, Yongrong Zuo, Sangsoo Ko, Nam-Seog Kim, Sangwook Han, Ikkyun Jo, Joonhee Lee, Juyoung Han, Daehyeon Kwon, Chulho Kim, Shinwoong Kim, Sang Won Son, Thomas Byunghak Cho:
A 14-nm 0.14-psrms Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration. IEEE J. Solid State Circuits 52(12): 3446-3457 (2017) - 2016
- [c7]Renaldi Winoto, Ashkan Olyaei, Mohammad Hajirostam, Wai Lau, Xiang Gao, Arnab Mitra, Ovidiu Carnu, Philip Godoy, Luns Tee, Hao Li, Erdem Erdogan, Alden Wong, Qiang Zhu, Timothy Loo, Fan Zhang, Liwei Sheng, Donghong Cui, Anuranjan Jha, Xiang Li, Wanghua Wu, Kun-Seok Lee, Derek Cheung, Ka Wo Pang, Haisong Wang, Jiexi Liu, Xingliang Zhao, Daibashish Gangopadhyay, David Cousinard, Arvind Anumula Paramanandam, Xiaoang Li, Norman Liu, Weiwei Xu, Yuan Fang, Xiaoyue Wang, Randy Tsang, Li Lin:
9.4 A 2×2 WLAN and Bluetooth combo SoC in 28nm CMOS with on-chip WLAN digital power amplifier, integrated 2G/BT SP3T switch and BT pulling cancelation. ISSCC 2016: 170-171 - [c6]Xiang Gao, Olivier Burg, Haisong Wang, Wanghua Wu, Cao-Thong Tu, Konstantinos Manetakis, Fan Zhang, Luns Tee, Mustafa Yayla, Sining Xiang, Randy Tsang, Li Lin:
9.6 A 2.7-to-4.3GHz, 0.16psrms-jitter, -246.8dB-FOM, digital fractional-N sampling PLL in 28nm CMOS. ISSCC 2016: 174-175 - 2015
- [c5]Xiang Gao, Luns Tee, Wanghua Wu, Kun-Seok Lee, Arvind Anumula Paramanandam, Anuranjan Jha, Norman Liu, Edwin Chan, Li Lin:
9.4 A 28nm CMOS digital fractional-N PLL with -245.5dB FOM and a frequency tripler for 802.11abgn/ac radio. ISSCC 2015: 1-3 - 2014
- [j4]Wanghua Wu, Robert Bogdan Staszewski, John R. Long:
A 56.4-to-63.4 GHz Multi-Rate All-Digital Fractional-N PLL for FMCW Radar Applications in 65 nm CMOS. IEEE J. Solid State Circuits 49(5): 1081-1096 (2014) - [c4]Wanghua Wu, Robert Bogdan Staszewski, John R. Long:
Design for test of a mm-Wave ADPLL-based transmitter. CICC 2014: 1-8 - 2013
- [j3]Wanghua Wu, John R. Long, Robert Bogdan Staszewski:
High-Resolution Millimeter-Wave Digitally Controlled Oscillators With Reconfigurable Passive Resonators. IEEE J. Solid State Circuits 48(11): 2785-2794 (2013) - [c3]Wanghua Wu, Xuefei Bai, Robert Bogdan Staszewski, John R. Long:
A 56.4-to-63.4GHz spurious-free all-digital fractional-N PLL in 65nm CMOS. ISSCC 2013: 352-353 - 2012
- [j2]John R. Long, Yi Zhao, Wanghua Wu, Marco Spirito, Leonardo Vera, Edward Gordon:
Passive Circuit Technologies for mm-Wave Wireless Systems on Silicon. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(8): 1680-1693 (2012) - 2011
- [c2]John R. Long, Yi Zhao, Y. Jin, Wanghua Wu, Marco Spirito:
Circuit technologies for mm-wave wireless systems on silicon. CICC 2011: 1-8
2000 – 2009
- 2008
- [j1]Wanghua Wu, Mihai A. T. Sanduleanu, Xia Li, John R. Long:
17 GHz RF Front-Ends for Low-Power Wireless Sensor Networks. IEEE J. Solid State Circuits 43(9): 1909-1919 (2008) - [c1]John R. Long, Wanghua Wu, Yunzhi Dong, Yi Zhao, Mihai A. T. Sanduleanu, John F. M. Gerrits, Gerrit van Veenendaal:
Energy-efficient wireless front-end concepts for ultra lower power radio. CICC 2008: 587-590
Coauthor Index
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