Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"A hybrid design-time/run-time scheduling flow to minimise the ..."

Javier Resano et al. (2004)

> Home

Details and statistics

DOI: 10.1016/J.MICPRO.2004.03.015

access: closed

type: Journal Article

metadata version: 2020-05-18

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/mam/ResanoVMVC04
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/mam/ResanoVMVC04
Javier Resano, Diederik Verkest, Daniel Mozos, Serge Vernalde, Francky Catthoor:
A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs. Microprocess. Microsystems 28(5-6): 291-301 (2004)

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.