"A variation aware timing model for a 2-input NAND gate and its use in ..."

Baljit Kaur et al. (2016)

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DOI: 10.1016/J.MEJO.2016.03.010

access: closed

type: Journal Article

metadata version: 2022-10-02

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Baljit Kaur, Arvind Kumar Sharma, Naushad Alam, S. K. Manhas, Bulusu Anand:
A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterization. Microelectron. J. 53: 45-55 (2016)

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