"A ±3.07% frequency variation clock generator implemented using HV ..."

Chua-Chin Wang et al. (2015)

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DOI: 10.1016/J.MEJO.2014.12.008

access: closed

type: Journal Article

metadata version: 2020-02-22

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Chua-Chin Wang, Deng-Shian Wang, Tzu-Chiao Sung, Yi-Jie Hsieh, Tzung-Je Lee:
A ±3.07% frequency variation clock generator implemented using HV CMOS process. Microelectron. J. 46(4): 285-290 (2015)

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