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"A Cost-Effective Latency-Aware Memory Bus for Symmetric Multiprocessor ..."

Jongsun Kim et al. (2008)

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DOI: 10.1109/TC.2008.96

access: closed

type: Journal Article

metadata version: 2019-09-25

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  persistent URL:
  - https://dblp.org/rec/journals/tc/KimLCV08
Jongsun Kim, Bo-Cheng Lai, Mau-Chung Frank Chang, Ingrid Verbauwhede:
A Cost-Effective Latency-Aware Memory Bus for Symmetric Multiprocessor Systems. IEEE Trans. Computers 57(12): 1714-1719 (2008)

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