"Study of 3-D Line Edge Roughness (LER) in Vertical Channel Array ..."

Jaehyuk Lim et al. (2025)

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DOI: 10.1109/TCAD.2025.3546195

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type: Journal Article

metadata version: 2025-09-11

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Jaehyuk Lim, Seokchan Yoon, Juho Sung, Sanghyun Kang, Gwon Kim, Hyoung Won Baac, Changhwan Shin:
Study of 3-D Line Edge Roughness (LER) in Vertical Channel Array Transistor for DRAM. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 44(9): 3571-3580 (2025)

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