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"Formal Modeling and Verification of Controllers for a Family of DRAM Caches."

Debiprasanna Sahoo et al. (2018)

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DOI: 10.1109/TCAD.2018.2857318

access: closed

type: Journal Article

metadata version: 2021-05-03

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  - https://dblp.org/rec/journals/tcad/SahooSSMRR18
Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam, S. Ramesh, Partha S. Roop:
Formal Modeling and Verification of Controllers for a Family of DRAM Caches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(11): 2485-2496 (2018)

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