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ORCIDIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 37
Volume 37, Number 1, January 2018
- Rajesh K. Gupta:
Editorial. 1-2 - Saraju P. Mohanty
, Michael Hübner, Chun Jason Xue, Xin Li, Hai Li:
Guest Editorial Circuit and System Design Automation for Internet of Things. 3-6 - Tosiron Adegbija, Anita Rogacs, Chandrakant Patel, Ann Gordon-Ross:
Microprocessor Optimizations for the Internet of Things: A Survey. 7-20 - Jian-Jun Han, Xin Tao, Dakai Zhu, Hakan Aydin, Zili Shao, Laurence T. Yang:
Multicore Mixed-Criticality Systems: Partitioned Scheduling and Utilization Bound. 21-34 - Kaiyuan Guo, Lingzhi Sui, Jiantao Qiu, Jincheng Yu, Junbin Wang, Song Yao, Song Han, Yu Wang, Huazhong Yang:
Angel-Eye: A Complete Design Flow for Mapping CNN Onto Embedded FPGA. 35-47 - Renzo Andri, Lukas Cavigelli, Davide Rossi, Luca Benini:
YodaNN: An Architecture for Ultralow Power Binary-Weight CNN Acceleration. 48-60 - Jonathan Beaumont, Andrey Mokhov, Danil Sokolov, Alex Yakovlev:
High-Level Asynchronous Concepts at the Interface Between Analog and Digital Worlds. 61-74 - Shaoming Chen, Lu Peng, Samuel Irving, Zhou Zhao, Weihua Zhang, Ashok Srivastava:
qSwitch: Dynamical Off-Chip Bandwidth Allocation Between Local and Remote Accesses. 75-87 - Juan Wang, Zhi Hong, Yuhan Zhang, Yier Jin:
Enabling Security-Enhanced Attestation With Intel SGX for Remote Terminal and IoT. 88-96 - Cédric Marchand, Lilian Bossuet, Ugo Mureddu, Nathalie Bochard, Abdelkarim Cherkaoui, Viktor Fischer:
Implementation and Characterization of a Physical Unclonable Function for IoT: A Case Study With the TERO-PUF. 97-109 - S. Dinesh Kumar, Himanshu Thapliyal, Azhar Mohammad:
FinSAL: FinFET-Based Secure Adiabatic Logic for Energy-Efficient and DPA Resistant IoT Devices. 110-122 - Hui Geng, Kevin A. Kwiat, Charles A. Kamhoua, Yiyu Shi:
On Random Dynamic Voltage Scaling for Internet-of-Things: A Game-Theoretic Approach. 123-132 - Andrea Cirigliano, Roberto Cordone, Alessandro Antonio Nacci, Marco Domenico Santambrogio:
Toward Smart Building Design Automation: Extensible CAD Framework for Indoor Localization Systems Deployment. 133-145 - Yilei Li, Kirti Dhwaj, Chien-Heng Wong, Yuan Du, Li Du, Yiwu Tang, Yiyu Shi, Tatsuo Itoh, Mau-Chung Frank Chang:
A Novel Fully Synthesizable All-Digital RF Transmitter for IoT Applications. 146-158 - Weiwei Shi, An Pan, Shi Yu, Chiu-sing Choy:
A Subthreshold Baseband Processor Core Design With Custom Modules and Cells for Passive RFID Tags. 159-167 - Congming Gao, Liang Shi, Cheng Ji, Yejia Di, Kaijie Wu, Chun Jason Xue, Edwin Hsing-Mean Sha:
Exploiting Parallelism for Access Conflict Minimization in Flash-Based Solid State Drives. 168-181 - Abhoy Kole, Kamalika Datta, Indranil Sengupta:
A New Heuristic for N-Dimensional Nearest Neighbor Realization of a Quantum Circuit. 182-192 - Andreas Grimmer, Werner Haselmayr, Andreas Springer, Robert Wille:
Design of Application-Specific Architectures for Networked Labs-on-Chips. 193-202 - Wenmian Hua, Rajit Manohar:
Exact Timing Analysis for Asynchronous Systems. 203-216 - Xiaotao Jia, Yici Cai, Qiang Zhou, Bei Yu:
A Multicommodity Flow-Based Detailed Router With Efficient Acceleration Techniques. 217-230 - Derong Liu, Bei Yu, Salim Chowdhury, David Z. Pan:
TILA-S: Timing-Driven Incremental Layer Assignment Avoiding Slew Violations. 231-244 - Taehee Lee, David Z. Pan, Joon-Sung Yang:
Clock Network Optimization With Multibit Flip-Flop Generation Considering Multicorner Multimode Timing Constraint. 245-256 - Dara Rahmati, Hamid Sarbazi-Azad:
Classified Round Robin: A Simple Prioritized Arbitration to Equip Best Effort NoCs With Effective Hard QoS. 257-269
Volume 37, Number 2, February 2018
- Jaya Dofe, Qiaoyan Yu:
Novel Dynamic State-Deflection Method for Gate-Level Design Obfuscation. 273-285 - Li Du, Chun-Chen Liu, Yan Zhang, Yilei Li, Yuan Du, Yen-Cheng Kuan, Mau-Chung Frank Chang:
A Single Layer 3-D Touch Sensing System for Mobile Devices Application. 286-296 - Tobias Schwarzer, Andreas Weichslgartner, Michael Glaß, Stefan Wildermann, Peter Brand, Jürgen Teich:
Symmetry-Eliminating Design Space Exploration for Hybrid Application Mapping on Many-Core Architectures. 297-310 - Lei Xie, Hoang Anh Du Nguyen, Mottaqiallah Taouil, Said Hamdioui, Koen Bertels:
A Mapping Methodology of Boolean Logic Circuits on Memristor Crossbar. 311-323 - A. N. Nagamani, S. N. Anuktha, N. Nanditha, Vinod Kumar Agrawal:
A Genetic Algorithm-Based Heuristic Method for Test Set Generation in Reversible Circuits. 324-336 - Insik Yoon, Arijit Raychowdhury:
Modeling and Analysis of Magnetic Field Induced Coupling on Embedded STT-MRAM Arrays. 337-349 - Hao Liang, Sharad Sinha, Wei Zhang:
Parallelizing Hardware Tasks on Multicontext FPGA With Efficient Placement and Scheduling Algorithms. 350-363 - Zhonghai Lu, Xueqian Zhao:
xMAS-Based QoS Analysis Methodology. 364-377 - Michele Lora, Sara Vinco, Enrico Fraccaroli, Davide Quaglia, Franco Fummi:
Analog Models Manipulation for Effective Integration in Smart System Virtual Platforms. 378-391 - Grace Li Zhang, Bing Li, Jinglan Liu, Yiyu Shi, Ulf Schlichtmann:
Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning. 392-405 - Stephan Held, Dirk Müller, Daniel Rotter, Rudolf Scheifele, Vera Traub, Jens Vygen:
Global Routing With Timing Constraints. 406-419 - Andrey Ayupov, Serif Yesil, Muhammet Mustafa Ozdal, Taemin Kim, Steven M. Burns, Ozcan Ozturk:
A Template-Based Design Methodology for Graph-Parallel Hardware Accelerators. 420-430 - Shouyi Yin, Zhicong Xie, Chenyue Meng, Peng Ouyang, Leibo Liu, Shaojun Wei:
Memory Partitioning for Parallel Multipattern Data Access in Multiple Data Arrays. 431-444 - Byunghoon Lee, Kwangsu Kim, Eui-Young Chung:
Replacement Policy Adaptable Miss Curve Estimation for Efficient Cache Partitioning. 445-457 - Kyuseung Han, Jae-Jin Lee, Jinho Lee, Woojoo Lee, Massoud Pedram:
TEI-NoC: Optimizing Ultralow Power NoCs Exploiting the Temperature Effect Inversion. 458-471 - Bo Mao, Suzhen Wu, Lide Duan:
Improving the SSD Performance by Exploiting Request Characteristics and Internal Parallelism. 472-484 - Tong-Yu Hsieh, Yi-Han Peng, Kuan-Chih Cheng:
Structural Variance-Based Error-Tolerability Test Method for Image Processing Applications. 485-498 - Arunkumar Vijayan, Saman Kiamehr, Mojtaba Ebrahimi, Krishnendu Chakrabarty, Mehdi Baradaran Tahoori:
Online Soft-Error Vulnerability Estimation for Memory Arrays and Logic Cores. 499-511 - Sumayya Shiraz, Osman Hasan:
A Library for Combinational Circuit Verification Using the HOL Theorem Prover. 512-516
Volume 37, Number 3, March 2018
- Ons Lahiouel, Mohamed H. Zaki, Sofiène Tahar:
Accelerated and Reliable Analog Circuits Yield Analysis Using SMT Solving Techniques. 517-530 - Yishi Yang, Hengliang Zhu, Zhaori Bi, Changhao Yan, Dian Zhou, Yangfeng Su, Xuan Zeng:
Smart-MSP: A Self-Adaptive Multiple Starting Point Optimization Approach for Analog Circuit Synthesis. 531-544 - Yoon Seok Yang, Hrishikesh Deshpande, Gwan Choi, Paul V. Gratz:
SDPR: Improving Latency and Bandwidth in On-Chip Interconnect Through Simultaneous Dual-Path Routing. 545-558 - Jae Hoon Lee, Min Soo Kim, Tae Hee Han:
Insertion Loss-Aware Routing Analysis and Optimization for a Fat-Tree-Based Optical Network-on-Chip. 559-572 - Yang Liu, Yuchen Zhou, Shiyan Hu:
Combating Coordinated Pricing Cyberattack and Energy Theft in Smart Home Cyber-Physical Systems. 573-586 - Debajyoti Bera:
Detection and Diagnosis of Single Faults in Quantum Circuits. 587-600 - Zipeng Li, Kelvin Yi-Tse Lai, John McCrone, Po-Hsien Yu, Krishnendu Chakrabarty, Miroslav Pajic, Tsung-Yi Ho, Chen-Yi Lee:
Efficient and Adaptive Error Recovery in a Micro-Electrode-Dot-Array Digital Microfluidic Biochip. 601-614 - Wajid Hassan Minhass, Jeffrey McDaniel, Michael Lander Raagaard, Philip Brisk, Paul Pop, Jan Madsen:
Scheduling and Fluid Routing for Flow-Based Microfluidic Laboratories-on-a-Chip. 615-628 - Dries Vercruyce, Elias Vansteenkiste, Dirk Stroobandt:
How Preserving Circuit Design Hierarchy During FPGA Packing Leads to Better Performance. 629-642 - Marco Donato, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky:
A Sub-Threshold Noise Transient Simulator Based on Integrated Random Telegraph and Thermal Noise Modeling. 643-656 - Yixiao Ding, Chris Chu, Wai-Kei Mak:
Self-Aligned Double Patterning-Aware Detailed Routing With Double Via Insertion and Via Manufacturability Consideration. 657-668 - Chau-Chin Huang, Hsin-Ying Lee, Bo-Qiao Lin, Sheng-Wei Yang, Chin-Hao Chang, Szu-To Chen, Yao-Wen Chang, Tung-Chieh Chen, Ismail Bustany:
NTUplace4dr: A Detailed-Routing-Driven Placer for Mixed-Size Circuit Designs With Technology and Region Constraints. 669-681 - Travis Boraten, Avinash Karanth Kodi:
Runtime Techniques to Mitigate Soft Errors in Network-on-Chip (NoC) Architectures. 682-695 - Mehran Mozaffari Kermani, Amir Jalali, Reza Azarderakhsh, Jiafeng Xie, Kim-Kwang Raymond Choo:
Reliable Inversion in GF(28) With Redundant Arithmetic for Secure Error Detection of Cryptographic Architectures. 696-704 - Yanchen Long, Zhonghai Lu, Haibin Shen:
Composable Worst-Case Delay Bound Analysis Using Network Calculus. 705-709 - Konrad Möller, Martin Kumm, Mario Garrido, Peter Zipf:
Optimal Shift Reassignment in Reconfigurable Constant Multiplication Circuits. 710-714
Volume 37, Number 4, April 2018
- Tao-Chun Yu, Shao-Yun Fang, Chia-Ching Chen, Yulong Sun, Poki Chen:
Device Array Layout Synthesis With Nonlinear Gradient Compensation for a High-Accuracy Current-Steering DAC. 717-728 - Xiaowei Xu, Feng Lin, Aosen Wang, Xinwei Yao, Qing Lu, Wenyao Xu, Yiyu Shi, Yu Hu:
Accelerating Dynamic Time Warping With Memristor-Based Customized Fabrics. 729-741 - Anirban Sengupta, Dipanjan Roy, Saraju P. Mohanty:
Triple-Phase Watermarking for Reusable IP Core Protection During Architecture Synthesis. 742-755 - Cheng Ji, Li-Pin Chang, Chao Wu, Liang Shi, Chun Jason Xue:
An I/O Scheduling Strategy for Embedded Flash Storage Devices With Mapping Cache. 756-769 - Hengliang Zhu, Feng Hu, Hao Zhou, David Z. Pan, Dian Zhou, Xuan Zeng:
Interlayer Cooling Network Design for High-Performance 3D ICs Using Channel Patterning and Pruning. 770-781 - Leibo Liu, Zhuoquan Zhou, Shaojun Wei, Min Zhu, Shouyi Yin, Shengyang Mao:
DRMaSV: Enhanced Capability Against Hardware Trojans in Coarse Grained Reconfigurable Architectures. 782-795 - Raouf Senhadji-Navarro, Ignacio Garcia-Vargas:
High-Performance Architecture for Binary-Tree-Based Finite State Machines. 796-805 - Mohammadreza Soltaniyeh, Ismail Kadayif, Ozcan Ozturk:
Classifying Data Blocks at Subpage Granularity With an On-Chip Page Table to Improve Coherence in Tiled CMPs. 806-819 - Morteza Gholipour, Ying-Yu Chen, Deming Chen:
Compact Modeling to Device- and Circuit-Level Evaluation of Flexible TMD Field-Effect Transistors. 820-831 - Mohamed Baker Alawieh, Fa Wang, Xin Li:
Identifying Wafer-Level Systematic Failure Patterns via Unsupervised Learning. 832-844 - Sheng-En David Lin, Dae Hyun Kim:
Detailed-Placement-Enabled Dynamic Power Optimization of Multitier Gate-Level Monolithic 3-D ICs. 845-854 - Sorin Dobre, Andrew B. Kahng, Jiajia Li:
Design Implementation With Noninteger Multiple-Height Cells for Improved Design Quality in Advanced Nodes. 855-868 - Wuxi Li, Shounak Dhar, David Z. Pan:
UTPlaceF: A Routability-Driven FPGA Placer With Physical and Congestion Aware Packing. 869-882 - Vasileios Tenentes, Daniele Rossi, S. Saqib Khursheed, Bashir M. Al-Hashimi, Krishnendu Chakrabarty:
Leakage Current Analysis for Diagnosis of Bridge Defects in Power-Gating Designs. 883-895 - Jiajia Chen, Chip-Hong Chang, Yujia Wang, Juan Zhao, Susanto Rahardja:
New Hardware and Power Efficient Sporadic Logarithmic Shifters for DSP Applications. 896-900 - Anita Aghaie, Mehran Mozaffari Kermani, Reza Azarderakhsh:
Reliable and Fault Diagnosis Architectures for Hardware and Software-Efficient Block Cipher KLEIN Benchmarked on FPGA. 901-905 - Jaeil Lim, Hyunggoy Oh, Heetae Kim, Sungho Kang:
Thermal Aware Test Scheduling for NTV Circuit. 906-910
Volume 37, Number 5, May 2018
- Szymon Szczesny:
HDL-Based Synthesis System With Debugger for Current-Mode FPAA. 915-926 - Jin Miao, Meng Li, Subhendu Roy, Yuzhe Ma, Bei Yu:
SD-PUF: Spliced Digital Physical Unclonable Function. 927-940 - Mengquan Li, Weichen Liu, Lei Yang, Peng Chen, Chao Chen:
Chip Temperature Optimization for Dark Silicon Many-Core Systems. 941-953 - Timo Feld, Frank Slomka:
Exact Interference of Tasks With Variable Rate-Dependent Behavior. 954-967 - Zipeng Li, Kelvin Yi-Tse Lai, Po-Hsien Yu, Krishnendu Chakrabarty, Tsung-Yi Ho, Chen-Yi Lee:
Structural and Functional Test Methods for Micro-Electrode-Dot-Array Digital Microfluidic Biochips. 968-981 - Giuseppe Tagliavini, Davide Rossi, Andrea Marongiu, Luca Benini:
Synergistic HW/SW Approximation Techniques for Ultralow-Power Parallel Computing. 982-995 - Alwin Zulehner, Robert Wille:
One-Pass Design of Reversible Circuits: Combining Embedding and Synthesis for Reversible Logic. 996-1008 - Lixue Xia, Boxun Li, Tianqi Tang, Peng Gu, Pai-Yu Chen, Shimeng Yu, Yu Cao, Yu Wang, Yuan Xie, Huazhong Yang:
MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System. 1009-1022 - Augusto Neutzling, Mayler G. A. Martins, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas:
A Simple and Effective Heuristic Method for Threshold Logic Identification. 1023-1036 - Mohammad Nazmus Sakib, Rakibul Hassan, Satyendra N. Biswas, Sunil R. Das:
Memristor-Based High-Speed Memory Cell With Stable Successive Read Operation. 1037-1049 - Mohamed Hassan, Hiren D. Patel:
MCXplore: Automating the Validation Process of DRAM Memory Controller Designs. 1050-1063 - Arunkumar Vijayan, Abhishek Koneru, Saman Kiamehr, Krishnendu Chakrabarty, Mehdi Baradaran Tahoori:
Fine-Grained Aging-Induced Delay Prediction Based on the Monitoring of Run-Time Stress. 1064-1075 - Amin Vali, Nicola Nicolici:
Bit-Flip Detection-Driven Selection of Trace Signals. 1076-1089 - Chih-Hao Wang, Tong-Yu Hsieh:
On Probability of Detection Lossless Concurrent Error Detection Based on Implications. 1090-1103 - Yansong Gao, Hua Ma, Said F. Al-Sarawi, Derek Abbott, Damith Chinthana Ranasinghe:
PUF-FSM: A Controlled Strong PUF. 1104-1108 - Tao Li, Qiang Liu:
A Low Cost Partial Scan Approach Based on Balanced Sequential Graph Transformation. 1109-1113
Volume 37, Number 6, June 2018
- Jack Tang, Mohamed Ibrahim, Krishnendu Chakrabarty, Ramesh Karri:
Secure Randomized Checkpointing for Digital Microfluidic Biochips. 1119-1132 - Chung-Han Chou, Tsui-Yun Chang, Kai-Chiang Wu, Shih-Chieh Chang:
Sensor-Based Time Speculation in the Presence of Timing Variability. 1133-1142 - Olga Krestinskaya, Timur Ibrayev, Alex Pappachen James:
Hierarchical Temporal Memory Features with Memristor Logic Circuits for Pattern Recognition. 1143-1156 - Qin Wang, Hao Zou, Hailong Yao, Tsung-Yi Ho, Robert Wille, Yici Cai:
Physical Co-Design of Flow and Control Layers for Flow-Based Microfluidic Biochips. 1157-1170 - Leibo Liu, Chen Yang, Shouyi Yin, Shaojun Wei:
CDPM: Context-Directed Pattern Matching Prefetching to Improve Coarse-Grained Reconfigurable Array Performance. 1171-1184 - Infall Syafalni, Tsutomu Sasao, Xiaoqing Wen:
A Method to Detect Bit Flips in a Soft-Error Resilient TCAM. 1185-1196 - Hsin-Ho Huang, Huimei Cheng, Chris Chu, Peter A. Beerel:
Area Optimization of Timing Resilient Designs Using Resynthesis. 1197-1210 - Zhibin Yu, Jing Wang, Lieven Eeckhout, Chengzhong Xu:
QIG: Quantifying the Importance and Interaction of GPGPU Architecture Parameters. 1211-1224 - Xiaoqing Xu, Yibo Lin, Meng Li, Tetsuaki Matsunawa, Shigeki Nojima, Chikaaki Kodama, Toshiya Kotani, David Z. Pan:
Subresolution Assist Feature Generation With Supervised Data Learning. 1225-1236 - Yibo Lin, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li, Charles J. Alpert, David Z. Pan:
MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes. 1237-1250 - Jian Kuang, Junjie Ye, Evangeline F. Y. Young:
STOMA: Simultaneous Template Optimization and Mask Assignment for Directed Self-Assembly Lithography With Multiple Patterning. 1251-1264 - Ying Wang, Huawei Li, Yinhe Han, Xiaowei Li:
A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multiprocessors. 1265-1277 - Irith Pomeranz:
Improving the Diagnosability of Scan Chain Faults Under Transparent-Scan by Observation Points. 1278-1287 - Yang Xue, Xin Li, Ronald D. Blanton:
Improving Diagnostic Resolution of Failing ICs Through Learning. 1288-1297 - Ryan Berryhill, Andreas G. Veneris:
Methodologies for Diagnosis of Unreachable States via Property Directed Reachability. 1298-1311 - Michael Shoniker, Oleg Oleynikov, Bruce F. Cockburn, Jie Han, Manish Rana, Witold Pedrycz:
Automatic Selection of Process Corner Simulations for Faster Design Verification. 1312-1316
Volume 37, Number 7, July 2018
- Sandeep Chatterjee, Valeriy Sukharev, Farid N. Najm:
Power Grid Electromigration Checking Using Physics-Based Models. 1317-1330 - Li Jiang, Tianjian Li, Naifeng Jing, Nam Sung Kim, Minyi Guo, Xiaoyao Liang:
CNFET-Based High Throughput SIMD Architecture. 1331-1344 - Daniele Rossi, Vasileios Tenentes, Sudhakar M. Reddy, Bashir M. Al-Hashimi, Andrew D. Brown:
Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories. 1345-1357 - Pengfei Qiu, Yongqiang Lyu, Jiliang Zhang, Dongsheng Wang, Gang Qu:
Control Flow Integrity Based on Lightweight Encryption Architecture. 1358-1369 - Xiaoming Chen, Qiaoyi Liu, Song Yao, Jia Wang, Qiang Xu, Yu Wang, Yongpan Liu, Huazhong Yang:
Hardware Trojan Detection in Third-Party Digital Intellectual Property Cores by Multilevel Feature Analysis. 1370-1383 - Minhui Zou, Xiaotong Cui, Liang Shi, Kaijie Wu:
Potential Trigger Detection for Hardware Trojans. 1384-1395