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"Two-dimensional IC layout compaction based on topological design rule ..."

John Valainis et al. (1990)

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DOI: 10.1109/43.46802

access: closed

type: Journal Article

metadata version: 2020-09-24

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John Valainis, Sinan Kaptanoglu, Erwin Liu, Roberto Suaya:
Two-dimensional IC layout compaction based on topological design rule checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(3): 260-275 (1990)

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