"High-Level Test Synthesis With Hierarchical Test Generation for ..."

Sying-Jyan Wang, Tung-Hua Yeh (2009)

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DOI: 10.1109/TCAD.2009.2026360

access: closed

type: Journal Article

metadata version: 2021-10-14

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Sying-Jyan Wang, Tung-Hua Yeh:
High-Level Test Synthesis With Hierarchical Test Generation for Delay-Fault Testability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(10): 1583-1596 (2009)

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