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ORCIDSying-Jyan Wang
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2020 – today
- 2024
[j21]Katherine Shu-Min Li, Fang-Chi Wu
, Jian-De Li, Sying-Jyan Wang:
Reinforcement Learning Double DQN for Chip-Level Synthesis of Paper-Based Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(8): 2465-2478 (2024)- 2023
- [j20]Jian-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho:
Design-for-reliability and on-the-fly fault tolerance procedure for paper-based digital microfluidic biochips with multiple faults. Integr. 89: 185-196 (2023) - [c67]Chun-Tsai Chien, Chien-Lung Wang, I-En Liao, Sying-Jyan Wang:
Implementing OIML R46 Communication Unit for DLMS/COSEM Security Suite 1 and Passing CTT V3.1 Test. ICNSC 2023: 1-6 - [c66]Nadun Sinhabahu, Katherine Shu-Min Li, Sying-Jyan Wang, J. R. Wang, Matt Ho:
Machine-Learning Driven Sensor Data Analytics for Yield Enhancement of Wafer Probing. ITC 2023: 93-98 - 2022
- [c65]Jian-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho:
Design-for-Reliability and Probability-Based Fault Tolerance for Paper-Based Digital Microfluidic Biochips with Multiple Faults. ASP-DAC 2022: 62-67 - [c64]Sying-Jyan Wang, Katherine Shu-Min Li, Chen-Yeh Lin, Song-Kong Chong:
Intrusion Detection and Obfuscation Mechanism for PUF-Based Authentication. ATS 2022: 90-95 - [c63]Nadun Sinhabahu, Jian-De Li, Katherine Shu-Min Li, Sying-Jyan Wang, Tsung-Yi Ho:
Trojan Insertions of Fully Programmable Valve Arrays. ETS 2022: 1-2 - [c62]Ken Chau-Cheung Cheng, Katherine Shu-Min Li, Sying-Jyan Wang, Andrew Yi-Ann Huang, Chen-Shiun Lee, Leon Li-Yang Chen, Peter Yi-Yu Liao, Nova Cheng-Yen Tsai:
Wafer Defect Pattern Classification with Explainable-Decision Tree Technique. ITC 2022: 549-553 - [c61]Nadun Sinhabahu, Katherine Shu-Min Li, Jian-De Li, J. R. Wang, Sying-Jyan Wang:
Yield-Enhanced Probe Head Cleaning with AI-Driven Image and Signal Integrity Pattern Recognition for Wafer Test. ITC 2022: 554-558 - [c60]Sying-Jyan Wang, Yen-Chang Shih, Katherine Shu-Min Li, Chen-Yeh Lin, Song-Kong Chong:
Improving IJTAG Test Efficiency and Security. VLSI-DAT 2022: 1-4 - 2021
- [j19]Sying-Jyan Wang, Yu-Sheng Chen, Katherine Shu-Min Li:
Modeling Attack Resistant PUFs Based on Adversarial Attack Against Machine Learning. IEEE J. Emerg. Sel. Topics Circuits Syst. 11(2): 306-318 (2021) - [c59]Fang-Chi Wu, Jian-De Li, Katherine Shu-Min Li, Sying-Jyan Wang, Tsung-Yi Ho:
Double DQN for Chip-Level Synthesis of Paper-Based Digital Microfluidic Biochips. DATE 2021: 350-353 - [c58]Katherine Shu-Min Li, Leon Li-Yang Chen, Ken Chau-Cheung Cheng, Peter Yi-Yu Liao, Sying-Jyan Wang, Andrew Yi-Ann Huang, Nova Cheng-Yen Tsai, Leon Chou, Gus Chang-Hung Han, Jwu E. Chen, Hsing-Chung Liang, Chun-Lung Hsu:
Automatic Inspection for Wafer Defect Pattern Recognition with Unsupervised Clustering. ETS 2021: 1-2 - [c57]Leon Li-Yang Chen, Katherine Shu-Min Li, Xu-Hao Jiang, Sying-Jyan Wang, Andrew Yi-Ann Huang, Jwu E. Chen, Hsing-Chung Liang, Chun-Lung Hsu:
Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling. ITC 2021: 208-212 - [c56]Peter Yi-Yu Liao, Katherine Shu-Min Li, Leon Li-Yang Chen, Sying-Jyan Wang, Andrew Yi-Ann Huang, Ken Chau-Cheung Cheng, Nova Cheng-Yen Tsai, Leon Chou:
WGrid: Wafermap Grid Pattern Recognition with Machine Learning Techniques. ITC 2021: 309-313 - [c55]Katherine Shu-Min Li, Leon Li-Yang Chen, Peter Yi-Yu Liao, Sying-Jyan Wang, Andrew Yi-Ann Huang, Ken Chau-Cheung Cheng:
Integrated Scratch Marker for Wafer Defect Diagnosis. ITC-Asia 2021: 1-4 - [c54]Sying-Jyan Wang, Tzu-Heng Chang, Katherine Shu-Min Li:
Machine Learning Assisted Challenge Selection for Modeling Attack Resistance in Strong PUFs. VLSI-DAT 2021: 1-4 - 2020
- [c53]Ken Chau-Cheung Cheng, Katherine Shu-Min Li, Andrew Yi-Ann Huang, Ji-Wei Li, Leon Li-Yang Chen, Nova Cheng-Yen Tsai, Sying-Jyan Wang, Chen-Shiun Lee, Leon Chou, Peter Yi-Yu Liao, Hsing-Chung Liang, Jwu E. Chen:
Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis. DATE 2020: 1710-1711 - [c52]Katherine Shu-Min Li, Peter Yi-Yu Liao, Leon Chou, Ken Chau-Cheung Cheng, Andrew Yi-Ann Huang, Sying-Jyan Wang, Gus Chang-Hung Han:
PWS: Potential Wafermap Scratch Defect Pattern Recognition with Machine Learning Techniques. ETS 2020: 1-6 - [c51]Sying-Jyan Wang, Cheng Xuan Cai, Yen-Wen Tseng, Katherine Shu-Min Li:
Feature Selection for Malicious Traffic Detection with Machine Learning. ICS 2020: 414-419 - [c50]Leon Li-Yang Chen, Katherine Shu-Min Li, Ken Chau-Cheung Cheng, Sying-Jyan Wang, Andrew Yi-Ann Huang, Leon Chou, Nova Cheng-Yen Tsai, Chen-Shiun Lee:
TestDNA-E: Wafer Defect Signature for Pattern Recognition by Ensemble Learning. ITC 2020: 1-4 - [c49]Jian-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho:
Watermarking for Paper-Based Digital Microfluidic Biochips. ITC-Asia 2020: 148-153 - [c48]Dyi-Chung Hu, Hirohito Hashimoto, Li-Fong Tseng, Ken Chau-Cheung Cheng, Katherine Shu-Min Li, Sying-Jyan Wang, Sean Y.-S. Chen, Jwu E. Chen, Clark Liu, Andrew Yi-Ann Huang:
Innovative Practice on Wafer Test Innovations. VTS 2020: 1
2010 – 2019
- 2019
- [j18]Sying-Jyan Wang, Kuan-Ting Yeh, Katherine Shu-Min Li:
Exploiting distribution of unknown values in test responses to optimize test output compactors. Integr. 65: 389-394 (2019) - [j17]Jian-De Li, Chun-Hao Kuo, Guan-Ruei Lu, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho, Hung-Ming Chen, Shiyan Hu:
Co-placement optimization in sensor-reusable cyber-physical digital microfluidic biochips. Microelectron. J. 83: 185-196 (2019) - [c47]Sying-Jyan Wang, Yu-Shen Chen, Katherine Shu-Min Li:
Adversarial Attack against Modeling Attack on PUFs. DAC 2019: 138 - [c46]Andrew Yi-Ann Huang, Katherine Shu-Min Li, Cheng-Yen Tsai, Ken Chau-Cheung Cheng, Sying-Jyan Wang, Xu-Hao Jiang, Leon Chou, Chen-Shiun Lee:
TestDNA: Novel Wafer Defect Signature for Diagnosis and Yield Learning. ITC 2019: 1-6 - 2018
- [c45]Jian-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho:
Digital Rights Management for Paper-Based Microfluidic Biochips. ATS 2018: 179-184 - [c44]Sying-Jyan Wang, Chin-Hung Lien, Katherine Shu-Min Li:
Register PUF with No Power-Up Restrictions. ISCAS 2018: 1-5 - [c43]Jia-Lin Wu, Katherine Shu-Min Li, Jain-De Li, Sying-Jyan Wang, Tsung-Yi Ho:
SOLAR: Simultaneous optimization of control-layer pins placement and channel routing in flow-based microfluidic biochips. VLSI-DAT 2018: 1-4 - 2017
- [j16]Katherine Shu-Min Li, Sying-Jyan Wang, Ruei-Ting Gu, Bo-Chuan Cheng:
Layout-Aware Optimized Prebond Silicon Interposer Test Synthesis. IEEE Des. Test 34(6): 77-83 (2017) - [j15]Katherine Shu-Min Li, Sying-Jyan Wang:
Design Methodology of Fault-Tolerant Custom 3D Network-on-Chip. ACM Trans. Design Autom. Electr. Syst. 22(4): 63:1-63:20 (2017) - [c42]Sying-Jyan Wang, Hsiang-Hsueh Chen, Chin-Hung Lien, Katherine Shu-Min Li:
Testing Clock Distribution Networks. ATS 2017: 163-168 - [c41]Jain-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho:
Design-for-testability for paper-based digital microfluidic biochips. DFT 2017: 1 - 2016
- [c40]Jain-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho:
Congestion- and timing-driven droplet routing for pin-constrained paper-based microfluidic biochips. ASP-DAC 2016: 593-598 - [c39]Sying-Jyan Wang, Ting-Jui Choi, Katherine Shu-Min Li:
Side-Channel Attack on Flipped Scan Chains. ATS 2016: 67-72 - [c38]Sying-Jyan Wang, Jhih-Yu Wei, Shih-Heng Huang, Katherine Shu-Min Li:
Test generation for combinational hardware Trojans. AsianHOST 2016: 1-6 - [c37]Jain-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho:
Test and diagnosis of paper-based microfluidic biochips. VTS 2016: 1-6 - 2014
- [c36]Katherine Shu-Min Li, Sying-Jyan Wang, Jia-Lin Wu, Cheng-You Ho, Yingchieh Ho, Ruei-Ting Gu, Bo-Chuan Cheng:
Optimized Pre-bond Test Methodology for Silicon Interposer Testing. ATS 2014: 13-18 - [c35]Sying-Jyan Wang, Che-Wei Kao, Katherine Shu-Min Li:
Improving Output Compaction Efficiency with High Observability Scan Chains. ATS 2014: 324-329 - [c34]Sying-Jyan Wang, Tsung-Huei Tzeng, Katherine Shu-Min Li:
Fast and accurate statistical static timing analysis. ISCAS 2014: 2555-2558 - 2013
- [j14]Nan-Cheng Lai, Sying-Jyan Wang:
Delay Test with Embedded Test Pattern Generator. J. Inf. Sci. Eng. 29(3): 545-556 (2013) - [c33]Yingchieh Ho, Katherine Shu-Min Li, Sying-Jyan Wang:
Leakage Monitoring Technique in Near-Threshold Systems with a Time-Based Bootstrapped Ring Oscillator. Asian Test Symposium 2013: 91-96 - [c32]Katherine Shu-Min Li, Cheng-You Ho, Ruei-Ting Gu, Sying-Jyan Wang, Yingchieh Ho, Jiun-Jie Huang, Bo-Chuan Cheng, An-Ting Liu:
A Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package. Asian Test Symposium 2013: 159-164 - [c31]Sying-Jyan Wang, Cheng-Hao Lin, Katherine Shu-Min Li:
Synthesis of 3D clock tree with pre-bond testability. ISCAS 2013: 2654-2657 - [c30]Yingchieh Ho, Katherine Shu-Min Li, Sying-Jyan Wang:
A 0.3 V low-power temperature-insensitive ring oscillator in 90 nm CMOS process. VLSI-DAT 2013: 1-4 - [c29]Sying-Jyan Wang, Yu-Siao Chen, Katherine Shu-Min Li:
Low-cost testing of TSVs in 3D stacks with pre-bond testable dies. VLSI-DAT 2013: 1-4 - 2012
- [j13]Tung-Hua Yeh, Sying-Jyan Wang:
Power-Aware High-Level Synthesis With Clock Skew Management. IEEE Trans. Very Large Scale Integr. Syst. 20(1): 167-171 (2012) - [c28]Bo-Chuan Cheng, Katherine Shu-Min Li, Sying-Jyan Wang:
De Bruijn graph-based communication modeling for fault tolerance in smart grids. APCCAS 2012: 623-626 - [c27]Sying-Jyan Wang, Han-Hsuan Hsu, Katherine Shu-Min Li:
Low-power delay test architecture for pre-bond test. ISCAS 2012: 2321-2324 - 2010
- [c26]Tung-Hua Yeh, Sying-Jyan Wang:
Thermal Safe High Level Test Synthesis for Hierarchical Testability. Asian Test Symposium 2010: 337-342
2000 – 2009
- 2009
- [j12]Sying-Jyan Wang, Katherine Shu-Min Li, Shih-Cheng Chen, Huai-Yan Shiu, Yun-Lung Chu:
Scan-Chain Partition for High Test-Data Compressibility and Low Shift Power Under Routing Constraint. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(5): 716-727 (2009) - [j11]Sying-Jyan Wang, Tung-Hua Yeh:
High-Level Test Synthesis With Hierarchical Test Generation for Delay-Fault Testability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(10): 1583-1596 (2009) - [c25]Sying-Jyan Wang, Kuo-Lin Fu, Katherine Shu-Min Li:
Low Peak Power ATPG for n-Detection Test. ISCAS 2009: 1993-1996 - [c24]Katherine Shu-Min Li, Ming-Hua Hsieh, Sying-Jyan Wang:
Level Converting Scan Flip-flops. ISCAS 2009: 2505-2508 - 2008
- [j10]Po-Chang Tsai, Sying-Jyan Wang:
Multi-mode-segmented scan architecture with layout-aware scan chain routing for test data and test time reduction. IET Comput. Digit. Tech. 2(6): 434-444 (2008) - [j9]Sying-Jyan Wang, Kuo-Lin Peng, Kuang-Cyun Hsiao, Katherine Shu-Min Li:
Layout-aware scan chain reorder for launch-off-shift transition test coverage. ACM Trans. Design Autom. Electr. Syst. 13(4): 64:1-64:16 (2008) - [c23]Nan-Cheng Lai, Sying-Jyan Wang:
On-Chip Test Generation Mechanism for Scan-Based Two-Pattern Tests. ATS 2008: 251-256 - [c22]Sying-Jyan Wang, Shih-Cheng Chen, Katherine Shu-Min Li:
Design and analysis of skewed-distribution scan chain partition for improved test data compression. ISCAS 2008: 2641-2644 - 2007
- [j8]Po-Chang Tsai, Sying-Jyan Wang, Ching-Hung Lin, Tung-Hua Yeh:
Test Data Compression for Minimum Test Application Time. J. Inf. Sci. Eng. 23(6): 1901-1909 (2007) - [c21]Sying-Jyan Wang, Po-Chang Tsai, Hung-Ming Weng, Katherine Shu-Min Li:
Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan Architecture. ATS 2007: 95-100 - [c20]Sying-Jyan Wang, Xin-Long Li, Katherine Shu-Min Li:
Layout-Aware Multi-Layer Multi-Level Scan Tree Synthesis. ATS 2007: 129-134 - [c19]Nan-Cheng Lai, Sying-Jyan Wang:
Low-Capture-Power Test Generation by Specifying A Minimum Set of Controlling Inputs. ATS 2007: 413-418 - [c18]Sying-Jyan Wang, Tung-Hua Yeh:
High-level test synthesis for delay fault testability. DATE 2007: 45-50 - [c17]Sying-Jyan Wang, Yan-Ting Chen, Katherine Shu-Min Li:
Low Capture Power Test Generation for Launch-off-Capture Transition Test Based on Don't-Care Filling. ISCAS 2007: 3683-3686 - 2006
- [j7]Nan-Cheng Lai, Sying-Jyan Wang, Y.-H. Fu:
Low-Power BIST With a Smoother and Scan-Chain Reorder Under Optimal Cluster Size. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11): 2586-2594 (2006) - [c16]Sying-Jyan Wang, Kuo-Lin Peng, Katherine Shu-Min Li:
Layout-Aware Scan Chain Reorder for Skewed-Load Transition Test Coverage. ATS 2006: 169-174 - [c15]Po-Chang Tsai, Sying-Jyan Wang:
Multi-Mode Segmented Scan Architecture with Layout-Aware Scan Chain Routing for Test Data and Test Time Reduction. ATS 2006: 225-230 - 2005
- [c14]Yu-Hsuan Fu, Sying-Jyan Wang:
Test Data Compression with Partial LFSR-Reseeding. Asian Test Symposium 2005: 343-347 - [c13]Mingchen Wen, Sying-Jyan Wang, Yen-Nan Lin:
Low power parallel multiplier with column bypassing. ISCAS (2) 2005: 1638-1641 - [c12]Po-Chang Tsai, Sying-Jyan Wang, Feng-Ming Chang:
FSM-based programmable memory BIST with macro command. MTDT 2005: 72-77 - 2004
- [c11]Nan-Cheng Lai, Sying-Jyan Wang, Yu-Hsuan Fu:
Low Power BIST with Smoother and Scan-Chain Reorder . Asian Test Symposium 2004: 40-45 - 2002
- [c10]Nan-Cheng Li, Sying-Jyan Wang:
A Reseeding Technique for LFSR-Based BIST Applications. Asian Test Symposium 2002: 200-205 - [c9]Yu-Lung Hsu, Sying-Jyan Wang:
Retiming-based logic synthesis for low-power. ISLPED 2002: 275-278 - 2001
- [j6]Sying-Jyan Wang:
Distributed Diagnosis in Multistage Interconnection Networks. J. Parallel Distributed Comput. 61(2): 254-264 (2001) - [c8]Sying-Jyan Wang, Sheng-Nan Chiou:
Generating Efficient Tests for Continuous Scan. DAC 2001: 162-165 - 2000
- [j5]Sying-Jyan Wang, Chia-Chun Lien:
Testability Improvement by Branch Point Control for Conditional Staements With Multiple Branches. J. Inf. Sci. Eng. 16(5): 719-731 (2000) - [c7]Sying-Jyan Wang, Chen-Jung Wei:
Efficient built-in self-test algorithm for memory. Asian Test Symposium 2000: 66-
1990 – 1999
- 1998
- [c6]Sying-Jyan Wang, Chao-Neng Huang:
Testing and Diagnosis of Interconnect Structures in FPGAs. Asian Test Symposium 1998: 283- - 1997
- [j4]Sying-Jyan Wang:
Distributed Routing in a Fault-Tolerant Multistage Interconnection Network. Inf. Process. Lett. 63(4): 205-210 (1997) - [c5]Sying-Jyan Wang, Tsi-Ming Tsai:
Test and diagnosis of fault logic blocks in FPGAs. ICCAD 1997: 722-727 - 1996
- [j3]Sying-Jyan Wang:
Load-Balancing in Multistage Interconnection Networks under Multiple-Pass Routing. J. Parallel Distributed Comput. 36(2): 189-194 (1996) - [c4]Po-Ching Hsu, Sying-Jyan Wang:
Testing And Diagnosis Of Board Interconnects In Microprocessor-Based Systems. Asian Test Symposium 1996: 56-61 - 1994
- [j2]Sying-Jyan Wang, Niraj K. Jha:
Algorithm-Based Fault Tolerance for FFT Networks. IEEE Trans. Computers 43(7): 849-854 (1994) - [c3]Sying-Jyan Wang:
Synthesis of Sequential Machines with Reduced Testing Cost. EDAC-ETC-EUROASIC 1994: 302-306 - 1993
- [j1]Niraj K. Jha, Sying-Jyan Wang:
Design and synthesis of self-checking VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(6): 878-887 (1993) - 1992
- [c2]Niraj K. Jha, Sying-Jyan Wang, Phillip C. Gripka:
Multiple Input Bridging Fault Detection in CMOS Sequential Circuits. ICCD 1992: 369-372 - 1991
- [c1]Niraj K. Jha, Sying-Jyan Wang:
Design and Synthesis of Self-Checking VLSI Circuits and Systems. ICCD 1991: 578-581
Coauthor Index
[j21] [j20] [c66] [c65] [c64] [c63] [c62] [c61] [c60] [j19] [c59] [c58] [c57] [c56] [c55] [c54] [c53] [c52] [c51] [c50] [c49] [c48] [j18] [j17] [c47] [c46] [c45] [c44] [c43] [j16] [j15] [c42] [c41] [c40] [c39] [c38] [c37] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [c29] [c28] [c27] [j12] [c25] [c24] [j9] [c22] [c21] [c20] [c17] [c16]
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