"High-Throughput LDPC-Decoder Architecture Using Efficient Comparison ..."

Sachin Kumawat et al. (2015)

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DOI: 10.1109/TCSI.2015.2403032

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type: Journal Article

metadata version: 2020-10-26

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Sachin Kumawat, Rahul Shrestha, Nikunj Daga, Roy P. Paily:
High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(5): 1421-1430 (2015)

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