default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDIEEE Transactions on Circuits and Systems - Part I: Regular Papers, Volume 62-I
Volume 62-I, Number 1, January 2015
- Kin Keung Lee, Tor Sverre Lande
, Philipp Dominik Häfliger:
A Sub-µW Bandgap Reference Circuit With an Inherent Curvature-Compensation Property. 1-9 - Yung-Hui Chung, Meng-Hsuan Wu, Hung-Sung Li:
A 12-bit 8.47-fJ/Conversion-Step Capacitor-Swapping SAR ADC in 110-nm CMOS. 10-18 - Haoran Yu, Kamal El-Sankary, Ezz I. El-Masry:
Distortion Analysis Using Volterra Series and Linearization Technique of Nano-Scale Bulk-Driven CMOS RF Amplifier. 19-28 - Dong Wu, Cencen Gao, Hui Liu, Nan Xie:
A Low Power Double-Sampling Extended Counting ADC With Class-AB OTA for Sensor Arrays. 29-38 - Behnam Sedighi, Xiaobo Sharon Hu, Huichu Liu, Joseph J. Nahas, Michael T. Niemier:
Analog Circuit Design Using Tunnel-FETs. 39-48 - John A. McNeill, Rabeeh Majidi, Jianping Gong:
"Split ADC" Background Linearization of VCO-Based ADCs. 49-58 - Chao-Chang Chiu, Po-Hsien Huang, Moris Lin, Ke-Horng Chen, Ying-Hsi Lin, Tsung-Yen Tsai, Chao-Cheng Lee:
A 0.6 V Resistance-Locked Loop Embedded Digital Low Dropout Regulator in 40 nm CMOS With 80.5% Power Supply Rejection Improvement. 59-69 - Jin-Yi Lin, Chih-Cheng Hsieh:
A 0.3 V 10-bit 1.17 f SAR ADC With Merge and Split Switching in 90 nm CMOS. 70-79 - Inhee Lee, Gunhee Han, Youngcheol Chae:
A 2 mW, 50 dB DR, 10 MHz BW 5 × Interleaved Bandpass Delta-Sigma Modulator at 50 MHz IF. 80-89 - Chun-Wei Hsu, Karthik Tripurari, Shih-An Yu, Peter R. Kinget:
A Sub-Sampling-Assisted Phase-Frequency Detector for Low-Noise PLLs With Robust Operation Under Supply Interference. 90-99 - Jaehyuk Choi, Jungsoon Shin, Byongmin Kang:
An Architecture With Pipelined Background Suppression and In-Situ Noise Cancelling for 2D/3D CMOS Image Sensor. 100-109 - Jiafeng Xie, Pramod Kumar Meher, Zhi-Hong Mao:
High-Throughput Finite Field Multipliers Using Redundant Basis for FPGA and ASIC Implementations. 110-119 - Chao Sun, Asuka Arakawa, Ken Takeuchi:
SEA-SSD: A Storage Engine Assisted SSD With Application-Coupled Simulation Platform. 120-129 - Nerhun Yildiz, Evren Cesur, Kamer Kayaer, Vedat Tavsanoglu, Murathan Alpay:
Architecture of a Fully Pipelined Real-Time Cellular Neural Network Emulator. 130-138 - Chao Wang, Jun Zhou, Roshan Weerasekera, Bin Zhao, Xin Liu, Philippe Royannez, Minkyu Je:
BIST Methodology, Architecture and Circuits for Pre-Bond TSV Testing in 3D Stacking IC Systems. 139-148 - Moshe Avital, Hadar Dagan, Itamar Levi, Osnat Keren, Alexander Fish:
DPA-Secured Quasi-Adiabatic Logic (SQAL) for Low-Power Passive RFID Tags Employing S-Boxes. 149-156 - Donald Donglong Chen, Nele Mentens, Frederik Vercauteren, Sujoy Sinha Roy, Ray C. C. Cheung, Derek Chi-Wai Pao, Ingrid Verbauwhede:
High-Speed Polynomial Multiplication Architecture for Ring-LWE and SHE Cryptosystems. 157-166 - Hisato Fujisaka, Takeshi Kamio, Chang-Jun Ahn, Masahiro Sakamoto, Kazuhisa Haeiwa:
A Sigma-Delta Domain Lowpass Wave Filter. 167-176 - Jesus Omar Lacruz, Francisco Garcia-Herrero, Javier Valls-Coquillat, David Declercq:
One Minimum Only Trellis Decoder for Non-Binary Low-Density Parity-Check Codes. 177-184 - Kang-Yi Fan, Pei-Yun Tsai:
An RLS Tracking and Iterative Detection Engine for Mobile MIMO-OFDM Systems. 185-194 - Aimin Jiang, Hon Keung Kwan, Yanping Zhu, Xiaofeng Liu, Ning Xu, Yibin Tang:
Design of Sparse FIR Filters With Joint Optimization of Sparsity and Filter Order. 195-204 - Gourav Saha, Ramkrishna Pasumarthy, Prathamesh Khatavkar:
Towards Analog Memristive Controllers. 205-214 - Shyam Prasad Adhikari, Hyongsuk Kim, Ram Kaji Budhathoki, Changju Yang, Leon O. Chua:
A Circuit-Based Learning Architecture for Multilayer Neural Networks With Memristor Bridge Synapses. 215-223 - Jiajia Chen, Chip-Hong Chang, Feng Feng, Weiao Ding, Jiatao Ding:
Novel Design Algorithm for Low Complexity Programmable FIR Filters Based on Extended Double Base Number System. 224-233 - Kim B. Ostman, Mikko Englund, Olli Viitala, Mikko Kaltiokallio, Kari Stadius, Kimmo Koli, Jussi Ryynänen:
Analysis and Design of N-Path Filter Offset Tuning in a 0.7-2.7-GHz Receiver Front-End. 234-243 - Soo-Hwan Shin, Soon-Jae Kweon, Seong-Hun Jo, Yong-Chang Choi, Sangyoub Lee, Hyung-Joun Yoo:
A 0.7-MHz-10-MHz CT+DT Hybrid Baseband Chain With Improved Passband Flatness for LTE Application. 244-253 - Ahmed Farouk Aref, Thomas M. Hone, Renato Negra:
A Study of the Impact of Delay Mismatch on Linearity of Outphasing Transmitters. 254-262 - Lammert Duipmans, Remko E. Struiksma, Eric A. M. Klumperink, Bram Nauta, Frank E. van Vliet:
Analysis of the Signal Transfer and Folding in N-Path Filters With a Series Inductance. 263-272 - Amin Ojani, Behzad Mesgarzadeh, Atila Alvandpour:
Monte Carlo-Free Prediction of Spurious Performance for ECDLL-Based Synthesizers. 273-282 - Basant Kumar Mohanty:
Novel Block-Formulation and Area-Delay-Efficient Reconfigurable Interpolation Filter Architecture for Multi-Standard SDR Applications. 283-291 - Chunshu Li, Min Li, Marian Verhelst, André Bourdoux, Liesbet Van der Perre, Sofie Pollin:
On the General Mathematical Framework, Calibration/Compensation Method, and Applications of Non-Ideal Software Defined Harmonics Rejection Transceivers. 292-301 - Hoang Nguyen, Johnson I. Agbinya, John Devlin:
FPGA-Based Implementation of Multiple Modes in Near Field Inductive Communication Using Frequency Splitting and MIMO Configuration. 302-310 - Yasuhiro Sugimoto, Toru Sai, Kei Watanabe, Mikio Abe:
Feedback Loop Analysis and Optimized Compensation Slope of the Current-Mode Buck DC-DC Converter in DCM. 311-319 - Weiguo Lu, Shuang Lang, Luowei Zhou, Herbert Ho-Ching Iu, Tyrone Fernando:
Improvement of Stability and Power Factor in PCM Controlled Boost PFC Converter With Hybrid Dynamic Compensation. 320-328 - Mohammad Saleh Tavazoei:
Comments on "Chaotic Characteristics Analysis and Circuit Implementation for a Fractional-Order System". 329-332 - Wan Mariam Wan Muda, Victor Sreeram, Ha Binh Minh, Abdul Ghafoor:
Comments on "Model-Order Reduction Using Variational Balanced Truncation With Spectral Shaping". 333-335
Volume 62-I, Number 2, February 2015
- Siamak Hafizi-Moori, Edmond Cretu:
Weakly-Coupled Resonators in Capacitive Readout Circuits. 337-346 - Samira Bashiri, Sadok Aouini, Naim Ben-Hamida, Calvin Plett:
Analysis and Modeling of the Phase Detector Hysteresis in Bang-Bang PLLs. 347-355 - Lei Sun, Bing Li, Alex K. Y. Wong, Wai Tung Ng, Kong-Pang Pun:
A Charge Recycling SAR ADC With a LSB-Down Switching Scheme. 356-365 - Yonghong Tao, Yong Lian:
A 0.8-V, 1-MS/s, 10-bit SAR ADC for Multi-Channel Neural Recording. 366-375 - Xin Meng, Yi Zhang, Tao He, Gabor C. Temes:
Low-Distortion Wideband Delta-Sigma ADCs With Shifted Loop Delays. 376-384 - Inna Vaisband, Mahmoud Saadat, Boris Murmann:
A Closed-Loop Reconfigurable Switched-Capacitor DC-DC Converter for Sub-mW Energy Harvesting Applications. 385-394 - Jinn-Shyan Wang, Chun-Yuan Cheng:
An All-Digital Delay-Locked Loop Using an In-Time Phase Maintenance Scheme for Low-Jitter Gigahertz Operations. 395-404 - Po-Hung Chen, Philex Ming-Yan Fan:
An 83.4% Peak Efficiency Single-Inductor Multiple-Output Based Adaptive Gate Biasing DC-DC Converter for Thermoelectric Energy Harvesting. 405-412 - Michele Caruso, Matteo Bassi, Andrea Bevilacqua, Andrea Neviani:
A 2-16 GHz 65 nm CMOS Stepped-Frequency Radar Transmitter With Harmonic Rejection for High-Resolution Medical Imaging Applications. 413-422 - Frédéric Broydé, Evelyne Clavelier:
Some Properties of Multiple-Antenna-Port and Multiple-User-Port Antenna Tuners. 423-432 - Ettore Lorenzo Firrao, Anne-Johan Annema, Frank E. van Vliet, Bram Nauta:
On the Minimum Number of States for Switchable Matching Networks. 433-440 - Bo Wang, Truc Quynh Nguyen, Anh-Tuan Do, Jun Zhou, Minkyu Je, Tony Tae-Hyoung Kim:
Design of an Ultra-low Voltage 9T SRAM With Equalized Bitline Leakage and CAM-Assisted Energy Efficiency Improvement. 441-448 - Maher Jridi, Ayman Alfalou, Pramod Kumar Meher:
A Generalized Algorithm and Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT. 449-457 - Mahsa Shoaran, Armin Tajalli, Massimo Alioto, Alexandre Schmid, Yusuf Leblebici:
Analysis and Characterization of Variability in Subthreshold Source-Coupled Logic Circuits. 458-467 - Insup Shin, Jae-Joon Kim, Youngsoo Shin:
Aggressive Voltage Scaling Through Fast Correction of Multiple Errors With Seamless Pipeline Operation. 468-477 - Kenichiro Cho, Takaya Miyano:
Chaotic Cryptography Using Augmented Lorenz Equations Aided by Quantum Key Distribution. 478-487 - Zdenek Biolek, Dalibor Biolek, Viera Biolková:
(Co)content in Circuits With Memristive Elements. 488-496 - Przemyslaw Mroszczyk, Piotr Dudek:
Trigger-Wave Asynchronous Cellular Logic Array for Fast Binary Image Processing. 497-506 - Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
A 7.92 Gb/s 437.2 mW Stochastic LDPC Decoder Chip for IEEE 802.15.3c Applications. 507-516 - Shahaboddin Moazzeni, Mohamad Sawan, Glenn E. R. Cowan:
An Ultra-Low-Power Energy-Efficient Dual-Mode Wake-Up Receiver. 517-526 - Tanbir Haque, Rabia Tugce Yazicigil, Kyle Jung-Lin Pan, John Wright, Peter R. Kinget:
Theory and Design of a Quadrature Analog-to-Information Converter for Energy-Efficient Wideband Spectrum Sensing. 527-535 - Ankush Goel, Behnam Analui, Hossein Hashemi:
Tunable Duplexer With Passive Feed-Forward Cancellation to Improve the RX-TX Isolation. 536-544 - Wei-Chang Liu, Ting-Chen Wei, Ya-Shiue Huang, Ching-Da Chan, Shyh-Jye Jou:
All-Digital Synchronization for SC/OFDM Mode of IEEE 802.15.3c and IEEE 802.11ad. 545-553 - Qiong Zou, Kaixue Ma, Kiat Seng Yeo:
A Low Phase Noise and Wide Tuning Range Millimeter-Wave VCO Using Switchable Coupled VCO-Cores. 554-563 - Joakim Osth, Magnus Karlsson, Adriana Serban, Shaofang Gong:
A Comparative Study of Single-Ended vs. Differential Six-Port Modulators for Wireless Communications. 564-570 - Maryam Jouzdani, Mohammad Mojtaba Ebrahimi, Karun Rawat, Mohamed Helaoui, Fadhel M. Ghannouchi:
Envelope Tracked Pulse Gate Modulated GaN HEMT Power Amplifier for Wireless Transmitters. 571-579 - Won Namgoong:
Adaptive and Robust Digital Harmonic-Reject Mixer With Optimized Local Oscillator Spacing. 580-589 - Juha Yli-Kaakinen, Vesa Lehtinen, Markku Renfors:
Multirate Charge-Domain Filter Design for RF-Sampling Multi-Standard Receiver. 590-599 - Chang-Jin Jeong, Yang Sun, Seok-Kyun Han, Sang-Gug Lee:
A 2.2 mW, 40 dB Automatic Gain Controllable Low Noise Amplifier for FM Receiver. 600-606 - Fabio Padovan, Marc Tiebout, Koen L. R. Mertens, Andrea Bevilacqua, Andrea Neviani:
Design of Low-Noise K-Band SiGe Bipolar VCOs: Theory and Implementation. 607-615
Volume 62-I, Number 3, March 2015
- Xing Li, Chi-Ying Tsui, Wing-Hung Ki:
Power Management Analysis of Inductively-Powered Implants with 1X/2X Reconfigurable Rectifier. 617-624 - Marius Neag, Raul Onet, István Kovács, Paul Martari:
Comparative Analysis of Simulation-Based Methods for Deriving the Phase- and Gain-Margins of Feedback Circuits With Op-Amps. 625-634 - Yongsun Lee, Mina Kim, Taeho Seong, Jaehyouk Choi:
A Low Phase Noise Injection-Locked Programmable Reference Clock Multiplier With a Two-Phase PVT-Calibrator for ΔΣ PLLs. 635-644 - Achille Donida, Remy Cellier, Angelo Nagari, Piero Malcovati, Andrea Baschirotto:
A 40-nm CMOS, 1.1-V, 101-dB Dynamic-Range, 1.7-mW Continuous-Time ΣΔ ADC for a Digital Closed-Loop Class-D Amplifier. 645-653 - Sudipta Sarkar, Yuan Zhou, Brian Elies, Yun Chiu:
PN-Assisted Deterministic Digital Background Calibration of Multistage Split-Pipelined ADC. 654-661 - Quanzhen Duan, Jeongjin Roh:
A 1.2-V 4.2- ppm°C High-Order Curvature-Compensated CMOS Bandgap Reference. 662-670 - Yao Liu, Reza Lotfi, Yongchang Hu, Wouter A. Serdijn:
A Comparative Analysis of Phase-Domain ADC and Amplitude-Domain IQ ADC. 671-679 - Anders Jakobsson, Adriana Serban, Shaofang Gong:
Implementation of Quantized-State System Models for a PLL Loop Filter Using Verilog-AMS. 680-688 - Zhangming Zhu, Zheng Qiu, Maliang Liu, Ruixue Ding:
A 6-to-10-Bit 0.5 V-to-0.9 V Reconfigurable 2 MS/s Power Scalable SAR ADC in 0.18 µm CMOS. 689-696 - Jun Zhou, Chao Wang, Xin Liu, Xin Zhang, Minkyu Je:
An Ultra-Low Voltage Level Shifter Using Revised Wilson Current Mirror for Fast and Energy-Efficient Wide-Range Voltage Conversion from Sub-Threshold to I/O Voltage. 697-706 - Yan Lu, Yipeng Wang, Quan Pan, Wing-Hung Ki, C. Patrick Yue:
A Fully-Integrated Low-Dropout Regulator With Full-Spectrum Power Supply Rejection. 707-716 - Ahmed Ashry, Diomadson Belfort, Hassan Aboushady:
Phase Noise Effect on Sine-Shaped Feedback DACs Used in Continuous-Time ΣΔ ADCs. 717-724 - Mark E. Halpern, David C. Ng:
Optimal Tuning of Inductive Wireless Power Links: Limits of Performance. 725-732 - Chenxin Zhang, Liang Liu, Dejan Markovic, Viktor Öwall:
A Heterogeneous Reconfigurable Cell Array for MIMO Signal Processing. 733-742 - Ming-Chiuan Su, Wei-Zen Chen, Pei-Si Wu, Yu-Hsian Chen, Chao-Cheng Lee, Shyh-Jye Jou:
A 10-Gb/s, 1.24 pJ/bit, Burst-Mode Clock and Data Recovery With Jitter Suppression. 743-751 - Chua-Chin Wang, Chih-Lin Chen, Zong-You Hou, Yi Hu, Jam-Wem Lee, Wan-Yen Lin, Yi-Feng Chang, Chia-Wei Hsu, Ming-Hsiang Song:
A 60 V Tolerance Transceiver With ESD Protection for FlexRay-Based Communication Systems. 752-760 - Katayoun Neshatpour, Mahdi Shabany, P. Glenn Gulak:
A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors. 761-770 - Shuhei Tanakamaru, Yuta Kitamura, Senju Yamazaki, Tsukasa Tokutomi, Ken Takeuchi:
Highly Reliable Coding Methods for Emerging Applications: Archive and Enterprise Solid-State Drives (SSDs). 771-780 - Taeho Seong, Jae Joon Kim, Jaehyouk Choi:
Analysis and Design of a Core-Size-Scalable Low Phase Noise LC-VCO for Multi-Standard Cellular Transceivers. 781-790 - Pere Palà-Schönwälder, Jordi Bonet-Dalmau, Alexis Lopez-Riera, F. Xavier Moncunill-Geniz, Francisco del Águìla López, M. Rosa Giralt-Mas:
Superregenerative Reception of Narrowband FSK Modulations. 791-798 - Xinmin Yu, Hooman Rashtian, Shahriar Mirabbasi, Partha Pratim Pande, Deuk Hyoun Heo:
An 18.7-Gb/s 60-GHz OOK Demodulator in 65-nm CMOS for Wireless Network-on-Chip. 799-806 - Shlomo Greenberg, Joseph Rabinowicz, Erez Manor:
Selective State Retention Power Gating Based on Formal Verification. 807-815 - Seongbo Shim, Jae Wook Lee, Youngsoo Shin:
An Analytical Approach to Thermal Design and Optimization With a Temperature-Dependent Power Model. 816-824 - Zhaomeng Cheng, Hai-Tao Zhang, Ming-Can Fan, Guanrong Chen:
Distributed Consensus of Multi-Agent Systems With Input Constraints: A Model Predictive Control Approach. 825-834 - Massimo Alioto, Elio Consoli, Gaetano Palumbo:
Variations in Nanometer CMOS Flip-Flops: Part II - Energy Variability and Impact of Other Sources of Variations. 835-843 - Shuhei Tanakamaru, Hiroki Yamazawa, Tsukasa Tokutomi, Sheyang Ning, Ken Takeuchi:
Design Methodology for Highly Reliable, High Performance ReRAM and 3-Bit/Cell MLC NAND Flash Solid-State Storage. 844-853 - Chiou-Yng Lee, Pramod Kumar Meher:
Efficient Subquadratic Space Complexity Architectures for Parallel MPB Single- and Double-Multiplications for All Trinomials Using Toeplitz Matrix-Vector Product Decomposition. 854-862 - Xin Lou, Ya Jun Yu, Pramod Kumar Meher:
Fine-Grained Critical Path Analysis and Optimization for Area-Time Efficient Realization of Multiple Constant Multiplications. 863-872 - María del Carmen Pérez, Rodrigo Garcia, Álvaro Hernández, Ana Jiménez, Cristina Diego, Jesús Ureña:
SoC-Based Architecture for an Ultrasonic Phased Array With Encoded Transmissions. 873-880 - Jiafeng Xie, Pramod Kumar Meher, Zhi-Hong Mao:
Low-Latency High-Throughput Systolic Multipliers Over GF(2m) for NIST Recommended Pentanomials. 881-890 - Maheshwar Pd. Sah, Changju Yang, Hyongsuk Kim, Bharathwaj Muthuswamy, Jovan Jevtic, Leon O. Chua:
A Generic Model of Memristors With Parasitic Components. 891-898 - Xiang Li, Pengchun Rao:
Synchronizing a Weighted and Weakly-Connected Kuramoto-Oscillator Digraph With a Pacemaker. 899-905 - Mika Laiho, Jennifer O. Hasler, Jiantao Zhou, Chao Du, Wei Lu, Eero Lehtonen, Jussi H. Poikonen:
FPAA/Memristor Hybrid Computing Infrastructure. 906-915 - Xin Zhang, Xinbo Ruan, Chi K. Tse:
Impedance-Based Local Stability Criterion for DC Distributed Power Systems. 916-925
Volume 62-I, Number 4, April 2015
- Ahmet Gokcen Mahmutoglu, Alper Demir:
Analysis of Low-Frequency Noise in Switched MOSFET Circuits: Revisited and Clarified. 929-937 - Shunta Iguchi, Pyungwoo Yeon, Hiroshi Fuketa, Koichi Ishida, Takayasu Sakurai, Makoto Takamiya:
Wireless Power Transfer With Zero-Phase-Difference Capacitance Control. 938-947 - Zohaib Hameed, Kambiz Moez:
A 3.2 V -15 dBm Adaptive Threshold-Voltage Compensated RF Energy Harvester in 130 nm CMOS. 948-956 - Thomas Souvignet, Bruno Allard, Xuefang Lin-Shi:
Sampled-Data Modeling of Switched- Capacitor Voltage Regulator With Frequency-Modulation Control. 957-966 - Lucas G. de Carli, Yuri Juppa, Adilson J. Cardoso, Carlos Galup-Montoro, Márcio C. Schneider:
Maximizing the Power Conversion Efficiency of Ultra-Low-Voltage CMOS Multi-Stage Rectifiers. 967-975 - Yao Zhu, Yuanjin Zheng, Yuan Gao, I. Made Darmayuda, Chengliang Sun, Minkyu Je, Alex Yuandong Gu:
An Energy Autonomous 400 MHz Active Wireless SAW Temperature Sensor Powered by Vibration Energy Harvesting. 976-985 - Kai Wang, Michael Z. Q. Chen:
Minimal Realizations of Three-Port Resistive Networks. 986-994 - Ding Nie, Bertrand M. Hochwald:
Broadband Matching Bounds for Coupled Loads. 995-1004 - Xinwang Zhang, Baoyong Chi, Zhihua Wang:
A 0.1-1.5 GHz Harmonic Rejection Receiver Front-End With Phase Ambiguity Correction, Vector Gain Calibration and Blocker-Resilient TIA. 1005-1014 - Peng Chen, Songbai He:
Investigation of Inverse Class-E Power Amplifier at Sub-Nominal Condition for Any Duty Ratio. 1015-1024 - Chak-Fong Cheang, Ka-Fai Un, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins:
A Combinatorial Impairment-Compensation Digital Predistorter for a Sub-GHz IEEE 802.11af-WLAN CMOS Transmitter Covering a 10x-Wide RF Bandwidth. 1025-1032 - Seyed Mohammadreza Fatemi, Mohammad Sharifkhani, Ali Fotowat-Ahmady:
A Unified Solution for Super-Regenerative Systems With Application to Correlator-Based UWB Transceivers. 1033-1041 - Fanta Chen, Jen-Ming Wu, Mau-Chung Frank Chang:
40-Gb/s 0.7-V 2: 1 MUX and 1: 2 DEMUX with Transformer-Coupled Technique for SerDes Interface. 1042-1051 - Thomas A. F. Theunisse, Jun Chai, Ricardo G. Sanfelice, W. P. M. H. Heemels:
Robust Global Stabilization of the DC-DC Boost Converter via Hybrid Control. 1052-1061 - Hanwool Jeong, Taewon Kim, Younghwi Yang, Taejoong Song, Gyu-Hong Kim, Hyo-Sig Won, Seong-Ook Jung:
Offset-Compensated Cross-Coupled PFET Bit-Line Conditioning and Selective Negative Bit-Line Write Assist for High-Density Low-Power SRAM. 1062-1070 - Indranil Hatai, Indrajit Chakrabarti, Swapna Banerjee:
An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis. 1071-1080 - Botang Shao, Peng Li:
Array-Based Approximate Arithmetic Computing: A General Model and Applications to Multiplier and Squarer Design. 1081-1090 - Chiou-Yng Lee, Pramod Kumar Meher:
Subquadratic Space-Complexity Digit-Serial Multipliers Over GF(2m) Using Generalized (a, b)-Way Karatsuba Algorithm. 1091-1098 - Chia-Hsiang Yang, Chun-Wei Chou, Chia-Shen Hsu, Chiao-En Chen:
A Systolic Array Based GTD Processor With a Parallel Algorithm. 1099-1108 - Kejie Huang, Rong Zhao, Yong Lian:
A Low Power and High Sensing Margin Non-Volatile Full Adder Using Racetrack Memory. 1109-1116 - Moslem Nouri, Arash Ahmadi, Shahpour Alirezaee, Gholamreza Karimi, Majid Ahmadi, Derek Abbott:
A Hopf Resonator for 2-D Artificial Cochlea: Piecewise Linear Model and Digital Implementation. 1117-1125 - Inhee Lee, Gyouho Kim, Suyoung Bang, Adriane Wolfe, Richard Bell, Seokhyeon Jeong, Yejoong Kim, Jeffrey Kagan, Meriah Arias-Thode, Bart Chadwick, Dennis Sylvester, David T. Blaauw, Yoonmyung Lee:
System-On-Mud: Ultra-Low Power Oceanic Sensing Platform Powered by Small-Scale Benthic Microbial Fuel Cells. 1126-1135 - Zhuo Wang, Robert E. Schapire, Naveen Verma:
Error Adaptive Classifier Boosting (EACB): Leveraging Data-Driven Training Towards Hardware Resilience for Signal Inference. 1136-1145 - Stephen Richardson, Dejan Markovic, Andrew Danowitz, John S. Brunhaver, Mark Horowitz:
Building Conflict-Free FFT Schedules. 1146-1155 - Riadul Islam, Matthew R. Guthaus:
Low-Power Clock Distribution Using a Current-Pulsed Clocked Flip-Flop. 1156-1164 - Alon Ascoli, Stefan Slesazeck, Hannes Mähne, Ronald Tetzlaff, Thomas Mikolajick:
Nonlinear Dynamics of a Locally-Active Memristor. 1165-1174 - Lucia Valentina Gambuzza, Arturo Buscarino, Luigi Fortuna, Mattia Frasca:
Memristor-Based Adaptive Coupling for Consensus and Synchronization. 1175-1184 - Hui Liu, Ming Cao, Chai Wah Wu, Junan Lu, Chi K. Tse:
Synchronization in Directed Complex Networks Using Graph Comparison Tools. 1185-1194 - Jiajing Wu, Chi K. Tse, Francis Chung-Ming Lau:
Concept of Node Usage Probability From Complex Networks and Its Applications to Communication Network Design. 1195-1204 - Jienan Chen, Jianhao Hu, Gerald E. Sobelman:
Stochastic Iterative MIMO Detection System: Algorithm and Hardware Design. 1205-1214
Volume 62-I, Number 5, May 2015
- Mario di Bernardo, Gianluca Setti, Wouter A. Serdijn, Yong Lian:
Guest Editorial Special Section on the 2014 IEEE International Symposium on Circuits and Systems (ISCAS 2014). 1217-1219 - Chenxin Zhang, Hemanth Prabhu, Yangxurui Liu, Liang Liu, Ove Edfors, Viktor Öwall:
Energy Efficient Group-Sort QRD Processor With On-Line Update for MIMO Channel Pre-Processing. 1220-1229 - Edwin Choque Pillco, Luís F. C. Alberto:
On the Foundations of Stability Analysis of Power Systems in Time Scales. 1230-1239 - Matthias Lorenz, Rudolf Ritter, Jens Anders, Maurits Ortmanns:
Estimation of Non-Idealities in Sigma-Delta Modulators for Test and Correction Using Unscented Kalman Filters. 1240-1249 - Kanupriya Bhardwaj, Thomas H. Lee:
A Phase-Interpolation and Quadrature-Generation Method Using Parametric Energy Transfer in CMOS. 1250-1259 - Russell Jeter, Igor Belykh:
Synchronization in On-Off Stochastic Networks: Windows of Opportunity. 1260-1269 - Hadi Heidari, Edoardo Bonizzoni, Umberto Gatti, Franco Maloberti:
A CMOS Current-Mode Magnetic Hall Sensor With Integrated Front-End. 1270-1278 - Wen Bin Ye, Ya Jun Yu:
Two-Step Optimization Approach for the Design of Multiplierless Linear-Phase FIR Filters. 1279-1287 - Keiji Kishine, Hiromi Inaba, Hiroshi Inoue, Makoto Nakamura, Akira Tsuchiya, Hiroaki Katsurai, Hidetoshi Onodera:
A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS. 1288-1295 - David E. Bellasi, Riccardo Rovatti, Luca Benini, Gianluca Setti:
A Low-Power Architecture for Punctured Compressed Sensing and Estimation in Wireless Sensor-Nodes. 1296-1305 - Benwei Xu, Yun Chiu:
Comprehensive Background Calibration of Time-Interleaved Analog-to-Digital Converters. 1306-1314 - Paolo Stefano Crovetti:
A Digital-Based Virtual Voltage Reference. 1315-1324 - Arindam Sanyal, Long Chen, Nan Sun:
Dynamic Element Matching With Signal-Independent Element Transition Rates for Multibit ΔΣ Modulators. 1325-1334 - Minsoo Choi, Jae-Yoon Sim, Hong-June Park, Byungsub Kim:
An Approximate Closed-Form Transfer Function Model for Diverse Differential Interconnects. 1335-1344 - Zisong Wang, Shengxi Diao, Lin He, Xicheng Jiang, Fujiang Lin:
Analysis of Current Efficiency for CMOS Class-B LC Oscillators. 1345-1352 - Darjn Esposito, Davide De Caro, Ettore Napoli, Nicola Petra, Antonio Giuseppe Maria Strollo:
Variable Latency Speculative Han-Carlson Adder. 1353-1361 - Minjie Lv, Hongbin Sun, Qiwei Ren, Bing Yu, Jingmin Xin, Nanning Zheng:
Logic-DRAM Co-Design to Exploit the Efficient Repair Technique for Stacked DRAM. 1362-1371 - Jun Han, Renfeng Dou, Lingyun Zeng, Shuai Wang, Zhiyi Yu, Xiaoyang Zeng:
A Heterogeneous Multicore Crypto-Processor With Flexible Long-Word-Length Computation. 1372-1381 - Yakov Kaplan, Shmuel Wimer:
Mixing Drivers in Clock-Tree for Power Supply Noise Reduction. 1382-1391 - Yibin Hong, Yong Lian:
A Memristor-Based Continuous-Time Digital FIR Filter for Biomedical Signal Processing. 1392-1401 - Yang Zhang, Yi Shen, Xiaoping Wang, Lina Cao:
A Novel Design for Memristor-Based Logic Switch and Crossbar Circuits. 1402-1411 - Padmanabhan Madampu Suryasarman, Andreas Springer:
A Comparative Analysis of Adaptive Digital Predistortion Algorithms for Multiple Antenna Transmitters. 1412-1420 - Sachin Kumawat, Rahul Shrestha, Nikunj Daga, Roy P. Paily:
High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule. 1421-1430 - Yushi Zhou, Norman M. Filiol, Fei Yuan:
A Quadrature Charge-Domain Sampling Mixer With Embedded FIR, IIR, and N-Path Filters. 1431-1440 - Ke Huang, Ziqiang Wang, Xuqiang Zheng, Chun Zhang, Zhihua Wang:
A 80 mW 40 Gb/s Transmitter With Automatic Serializing Time Window Search and 2-tap Pre-Emphasis in 65 nm CMOS Technology. 1441-1450
Volume 62-I, Number 6, June 2015
- Alfio Dario Grasso, Davide Marano, Gaetano Palumbo, Salvatore Pennisi:
Design Methodology of Subthreshold Three-Stage CMOS OTAs Suitable for Ultra-Low-Power Low-Area and High Driving Capability. 1453-1462 - Marijn Verbeke, Pieter Rombouts, Arno Vyncke, Guy Torfs:
Influence of Jitter on Limit Cycles in Bang-Bang Clock and Data Recovery Circuits. 1463-1471 - Dae Hyun Kwon, Young-Seok Park, Woo-Young Choi:
A clock and data recovery circuit with programmable multi-level phase detector characteristics and a built-in jitter monitor. 1472-1480 - Hussein Adel, Marc Sabut, Marie-Minerve Louërat:
Split ADC Based Fully Deterministic Multistage Calibration for High Speed Pipeline ADCs. 1481-1488 - Sha Tao, Ana Rusu:
A Power-Efficient Continuous-Time Incremental Sigma-Delta ADC for Neural Recording Systems. 1489-1498 - Wenjie Feng, Wenquan Che, Quan Xue:
Balanced filters with wideband common mode suppression using dual-mode ring resonators. 1499-1507 - Yinan Wang, Håkan Johansson, Hui Xu, Zhaolin Sun:
Joint Blind Calibration for Mixed Mismatches in Two-Channel Time-Interleaved ADCs. 1508-1517 - Roberto Gómez-García, Raul Loeches-Sanchez, Dimitra Psychogiou, Dimitrios Peroulis:
Single/multi-band Wilkinson-type power dividers with embedded transversal filtering sections and application to channelized filters. 1518-1527 - Ping-Hsuan Hsieh, Chih-Hsien Chou, Tao Chiang:
An RF Energy Harvester With 44.1% PCE at Input Available Power of -12 dBm. 1528-1537 - Younghwi Yang, Juhyun Park, Seung Chul Song, Joseph Wang, Geoffrey Yeap, Seong-Ook Jung:
SRAM Design for 22-nm ETSOI Technology: Selective Cell Current Boosting and Asymmetric Back-Gate Write-Assist Circuit. 1538-1545 - Samer Houri, Gérard Billiot, Marc Belleville, Alexandre Valentian, Hervé Fanet:
Limits of CMOS Technology and Interest of NEMS Relays for Adiabatic Logic Applications. 1546-1554 - Hanwool Jeong, Taewon Kim, Kyoman Kang, Taejoong Song, Gyu-Hong Kim, Hyo-Sig Won, Seong-Ook Jung:
Switching pMOS Sense Amplifier for High-Density Low-Voltage Single-Ended SRAM. 1555-1563 - Byung-Do Yang:
Low-Power and Area-Efficient Shift Register Using Pulsed Latches. 1564-1571 - Shin-Chi Lai, Chih-Hao Liu, Ling-Yi Wang, Shin-Hao Chen, Ke-Horng Chen:
11.25-ms-Group-Delay and Low-Complexity Algorithm Design of 18-Band Quasi-ANSI S1.11 1/3 Octave Digital Filterbank for Hearing Aids. 1572-1581 - Chien-Cheng Tseng, Su-Ling Lee:
Designs of Discrete-Time Generalized Fractional Order Differentiator, Integrator and Hilbert Transformer. 1582-1590 - Paolo Maffezzoni, Bichoy Bahr, Zheng Zhang, Luca Daniel:
Oscillator Array Models for Associative Memory and Pattern Recognition. 1591-1598 - Hai-Tao Zhang, Zhaomeng Cheng, Guanrong Chen, Chunguang Li:
Model predictive flocking control for second-order multi-agent systems with input constraints. 1599-1606 - Dongsheng Yu, Herbert Ho-Ching Iu, Yan Liang, Tyrone Fernando, Leon O. Chua:
Dynamic Behavior of Coupled Memristor Circuits. 1607-1616 - Yi-Da Wu, Hsin Chen:
The Diffusion Network in Analog VLSI Exploiting Noise-Induced Stochastic Dynamics to Regenerate Various Continuous Paths. 1617-1626 - Hugo Cruz, Hong-Yi Huang, Shuenn-Yuh Lee, Ching-Hsing Luo:
A 1.3 mW low-IF, current-reuse, and current-bleeding RF front-end for the MICS band with sensitivity of -97 dbm. 1627-1636 - Yi Fang, Lin Wang, Pingping Chen, Jing Xu, Guanrong Chen, Weikai Xu:
Design and Analysis of a DCSK-ARQ/CARQ System Over Multipath Fading Channels. 1637-1647 - Jooseung Kim, Dongsu Kim, Yunsung Cho, Daehyun Kang, Byungjoon Park, Kyunghoon Moon, Seungbeom Koo, Bumman Kim:
Highly Efficient RF Transmitter Over Broad Average Power Range Using Multilevel Envelope-Tracking Power Amplifier. 1648-1657 - Mohammad Sadegh Jalali, Clifford Ting, Joshua Liang, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura:
A 3x blind ADC-based CDR for a 20 dB loss channel. 1658-1667 - Vincenzo Fiore, Placido Battiato, Sahel Abdinia, Stéphanie Jacobs, Isabelle Chartier, Romain Coppard, Gerhard Klink, Eugenio Cantatore, Egidio Ragonese, Giuseppe Palmisano:
An Integrated 13.56-MHz RFID Tag in a Printed Organic Complementary TFT Technology on Flexible Substrate. 1668-1677 - Edward K. F. Lee:
A Discrete Controlled Fully Integrated Class E Coil Driver With Power Efficient ASK Modulation for Powering Biomedical Implants. 1678-1687
Volume 62-I, Number 7, July 2015
- Yi Zhang, Chia-Hung Chen, Tao He, Gabor C. Temes:
A Continuous-Time Delta-Sigma Modulator for Biomedical Ultrasound Beamformer Using Digital ELD Compensation and FIR Feedback. 1689-1698 - Rui Wang, Deping Huang, Tianshi He, Jinghong Chen, Yang You, Ping Gui:
Effect of OPAMP Input Offset on Continuous-Time ΔΣ Modulators With Current-Mode DACs. 1699-1706 - Haiyang Zhu, Ron Kapusta, Yong-Bin Kim:
Noise Reduction Technique Through Bandwidth Switching for Switched-Capacitor Amplifier. 1707-1715 - Mo Huang, Dihu Chen, Jianping Guo, Hui Ye, Ken Xu, Xiaofeng Liang, Yan Lu:
A CMOS Delta-Sigma PLL Transmitter with Efficient Modulation Bandwidth Calibration. 1716-1725 - Ramses Pierco, Guy Torfs, Jochen Verbrugghe, Benoit Bakeroot, Johan Bauwelinck:
A 16 Channel High-Voltage Driver with 14 Bit Resolution for Driving Piezoelectric Actuators. 1726-1736 - Eleonora Franchi Scarselli, Luca Perilli, Luca Perugini, Roberto Canegallo:
A 40 nm CMOS I/O Pad Design With Embedded Capacitive Coupling Receiver for Non-Contact Wafer Probe Test. 1737-1746 - Enrico Macrelli, Aldo Romani, Rudi Paolo Paganelli, Antonio Camarda, Marco Tartagni:
Design of Low-Voltage Integrated Step-up Oscillators with Microtransformers for Energy Harvesting Applications. 1747-1756 - Erya Deng, Yue Zhang, Wang Kang, Bernard Dieny, Jacques-Olivier Klein, Guillaume Prenat, Weisheng Zhao:
Synchronous 8-bit Non-Volatile Full-Adder based on Spin Transfer Torque Magnetic Tunnel Junction. 1757-1765 - Ignatius Bezzam, Chakravarthy Mathiazhagan, Tezaswi Raja, Shoba Krishnan:
An Energy-Recovering Reconfigurable Series Resonant Clocking Scheme for Wide Frequency Operation. 1766-1775 - Byungkyu Song, Taehui Na, Jisu Kim, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung:
Latch Offset Cancellation Sense Amplifier for Deep Submicrometer STT-RAM. 1776-1784 - Vikram B. Suresh, Wayne P. Burleson:
Entropy and Energy Bounds for Metastability Based TRNG with Lightweight Post-Processing. 1785-1793 - Yu-Min Lin, Huai-Ting Li, Ming-Han Chung, An-Yeu Wu:
Byte-Reconfigurable LDPC Codec Design With Application to High-Performance ECC of NAND Flash Memory Systems. 1794-1804 - Mohsen Hayati, Moslem Nouri, Saeed Haghiri, Derek Abbott:
Digital Multiplierless Realization of Two Coupled Biological Morris-Lecar Neuron Model. 1805-1814 - Alireza Mehrnia, Alan N. Willson Jr.:
Further Desensitized FIR Halfband Filters. 1815-1824 - Michele Scarpiniti, Danilo Comminiello, Raffaele Parisi, Aurelio Uncini:
Novel Cascade Spline Architectures for the Identification of Nonlinear Systems. 1825-1835 - Kexin Liu, Henghui Zhu, Jinhu Lu:
Bridging the Gap Between Transmission Noise and Sampled Data for Robust Consensus of Multi-Agent Systems. 1836-1844 - Antonio Buonomo, Alessandro Lo Schiavo:
Analysis and Design of Dual-Mode CMOS LC-VCOs. 1845-1853 - Osama Ullah Khan, David D. Wentzloff:
8.1 nJ/b 2.4 GHz Short-Range Communication Receiver in 65 nm CMOS. 1854-1862 - Reza Meraji, S. M. Yasser Sherazi, John B. Anderson, Henrik Sjöland, Viktor Öwall:
Low Power Analog and Digital (7, 5) Convolutional Decoders in 65 nm CMOS. 1863-1872 - Ting-Kuei Kuan, Shen-Iuan Liu:
A Loop Gain Optimization Technique for Integer-N TDC-Based Phase-Locked Loops. 1873-1882 - Hyunji Koo, Choul-Young Kim, Songcheol Hong:
Design and Analysis of 239 GHz CMOS Push-Push Transformer-Based VCO With High Efficiency and Wide Tuning Range. 1883-1893
Volume 62-I, Number 8, August 2015
- José M. de la Rosa, Patrick Chiang, Lawrence T. Clark:
Guest Editorial: Special Section on the 2014 IEEE Custom Integrated Circuits Conference (CICC 2014). 1897-1898 - Ning Lu, Richard A. Wachnik:
Modeling of Resistance in FinFET Local Interconnect. 1899-1907 - Ji-Eun Jang, Jaeha Kim:
PPV-Based Modeling and Event-Driven Simulation of Injection-Locked Oscillators in SystemVerilog. 1908-1917 - Jorge Zarate-Roldan, Salvador Carreon-Bautista, Alfredo Costilla-Reyes, Edgar Sánchez-Sinencio:
A Power Management Unit With 40 dB Switching-Noise-Suppression for a Thermal Harvesting Array. 1918-1928 - Sandipan Kundu, Erkan Alpman, Julia Hsin-Lin Lu, Hasnain Lakdawala, Jeyanandh Paramesh, Byunghoo Jung, Sarit Zur, Eshel Gordon:
A 1.2 V 2.64 GS/s 8 bit 39 mW Skew-Tolerant Time-interleaved SAR ADC in 40 nm Digital LP CMOS for 60 GHz WLAN. 1929-1939 - Osama Elhadidy, Sherif Shakib, Keith Krenek, Samuel Palermo, Kamran Entesari:
A Wide-Band Fully-Integrated CMOS Ring-Oscillator PLL-Based Complex Dielectric Spectroscopy System. 1940-1949 - Jaebin Choi, Eyal Aklimi, Chen Shi, David Tsai, Harish Krishnaswamy, Kenneth L. Shepard:
Matching the Power, Voltage, and Size of Biological Systems: A nW-Scale, 0.023-mm3 Pulsed 33-GHz Radio Transmitter Operating From a 5 kT/q-Supply Voltage. 1950-1958 - Edward M. Cherry:
Gain at an Arbitrary Cut in a Linear Bilateral Network, and Its Relation to Loop Gain in Feedback Amplifiers. 1959-1970 - Mohammad Hossein Taghavi, Leonid Belostotski, James W. Haslett, Peyman Ahmadi:
10-Gb/s 0.13-µm CMOS Inductorless Modified-RGC Transimpedance Amplifier. 1971-1980 - Torsten Djurhuus, Viktor Krozer:
A Generalized Model of Noise Driven Circuits with Application to Stochastic Resonance. 1981-1990 - Dongsheng Liu, Huan Lin, Xuecheng Zou, Liang Guo, Ke Yao, Zilong Liu:
A High Sensitivity Analog Front-end Circuit for Semi-Passive HF RFID Tag Applied to Implantable Devices. 1991-2002 - Yi-Keng Hsieh, Ya-Ru Wu, Po-Chih Ku, Liang-Hung Lu:
An Analog On-Line Gain Calibration Loop for RF Amplifiers. 2003-2012 - Colin Weltin-Wu, Eythan Familier, Ian Galton:
A Linearized Model for the Design of Fractional-N Digital PLLs Based on Dual-Mode Ring Oscillator FDCs. 2013-2023 - Meilin Wan, Zhangqing He, Shuang Han, Kui Dai, Xuecheng Zou:
An Invasive-Attack-Resistant PUF Based On Switched-Capacitor Circuit. 2024-2034 - Massimo Alioto, Elio Consoli, Gaetano Palumbo:
Variations in Nanometer CMOS Flip-Flops: Part I - Impact of Process Variations on Timing. 2035-2043 - Chung-Hsin Liu, Chiou-Yng Lee, Pramod Kumar Meher:
Efficient Digit-Serial KA-Based Multiplier Over Binary Extension Fields Using Block Recombination Approach. 2044-2051 - Wen-Quan He, Yuan-Ho Chen, Shyh-Jye Jou:
High-Accuracy Fixed-Width Booth Multipliers Based on Probability and Simulation. 2052-2061 - Anirudh Srikant Iyengar, Swaroop Ghosh, Jae-Won Jang:
MTJ-Based State Retentive Flip-Flop With Enhanced-Scan Capability to Sustain Sudden Power Failure. 2062-2068 - Itamar Levi, Osnat Keren, Alexander Fish:
Data-Dependent Delays as a Barrier Against Power Attacks. 2069-2078 - Manish Kumar Jaiswal, B. Sharat Chandra Varma, Hayden Kwok-Hay So, M. Balakrishnan, Kolin Paul, Ray C. C. Cheung:
Configurable Architectures for Multi-Mode Floating Point Adders. 2079-2090 - Junyoung Ko, Jisu Kim, Youngdon Choi, Hyun Kook Park, Seong-Ook Jung:
Temperature-Tracking Sensing Scheme With Adaptive Precharge and Noise Compensation Scheme in PRAM. 2091-2102 - Maurizio Martina, Guido Masera, Massimo Ruo Roch, Gianluca Piccinini:
Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT. 2103-2113 - Iman Madadi, Massoud Tohidian, Robert Bogdan Staszewski:
Analysis and Design of I/Q Charge-Sharing Band-Pass-Filter for Superheterodyne Receivers. 2114-2121 - Atsutake Kosuge, Shu Ishizuka, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda:
Analysis and Design of an 8.5-Gb/s/Link Multi-Drop Bus Using Energy-Equipartitioned Transmission Line Couplers. 2122-2131
Volume 62-I, Number 9, September 2015
- Apisak Worapishet, Andreas Demosthenous:
Generalized Analysis of Random Common-Mode Rejection Performance of CMOS Current Feedback Instrumentation Amplifiers. 2137-2146 - Junan Lee, Himchan Park, Bongsub Song, Kiwoon Kim, Jaeha Eom, Kyunghoon Kim, Jinwook Burm:
High Frame-Rate VGA CMOS Image Sensor Using Non-Memory Capacitor Two-Step Single-Slope ADCs. 2147-2155 - Yun-Rae Jo, Seong-Kwan Hong, Oh-Kyong Kwon:
A Multi-Bit Incremental ADC Based on Successive Approximation for Low Noise and High Resolution Column-Parallel Readout Circuits. 2156-2166 - Zhangming Zhu, Yuhua Liang:
A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC in 0.18- μm CMOS for Medical Implant Devices. 2167-2176 - Ismail Cevik, Suat U. Ay:
An Ultra-Low Power Energy Harvesting and Imaging (EHI) Type CMOS APS Imager With Self-Power Capability. 2177-2186 - Robert D'Angelo, Sameer R. Sonkusale:
A Time-Mode Translinear Principle for Nonlinear Analog Computation. 2187-2195 - Jianyu Zhong, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
Thermal and Reference Noise Analysis of Time-Interleaving SAR and Partial-Interleaving Pipelined-SAR ADCs. 2196-2206 - Paolo Maffezzoni, Luca Daniel, Nikhil Shukla, Suman Datta, Arijit Raychowdhury:
Modeling and Simulation of Vanadium Dioxide Relaxation Oscillators. 2207-2215 - Jiageng Huang, Shiliang Yang, George Jie Yuan:
A 75 dB SNDR 10-MHz Signal Bandwidth Gm-C-Based Sigma-Delta Modulator With a Nonlinear Feedback Compensation Technique. 2216-2226 - Congyin Shi, Edgar Sánchez-Sinencio:
150-850 MHz High-Linearity Sine-wave Synthesizer Architecture Based on FIR Filter Approach and SFDR Optimization. 2227-2237 - Marco Cannizzaro, Salomon Beer, Jordi Cortadella, Ran Ginosar, Luciano Lavagno:
SafeRazor: Metastability-Robust Adaptive Clocking in Resilient Circuits. 2238-2247 - Thian Fatt Tay, Chip-Hong Chang, Leonel Sousa:
Base Transformation With Injective Residue Mapping for Dynamic Range Reduction in RNS. 2248-2259 - Yaara Neumeier, Y. Pesso, Osnat Keren:
Efficient Implementation of Punctured Parallel Finite Field Multipliers. 2260-2267 - Simran Singh, Lauri Anttila, Michael Epp, Wolfgang Schlecker, Mikko Valkama:
Frequency Response Mismatches in 4-channel Time-Interleaved ADCs: Analysis, Blind Identification, and Correction. 2268-2279 - Salvatore Caporale, Fabio Pareschi, Valerio Cambareri, Riccardo Rovatti, Gianluca Setti:
A Soft-Defined Pulse Width Modulation Approach - Part I: Principles. 2280-2289 - Salvatore Caporale, Fabio Pareschi, Valerio Cambareri, Riccardo Rovatti, Gianluca Setti:
A Soft-Defined Pulse Width Modulation Approach - Part II: System Modeling. 2290-2300 - Jingyuan Zhan, Xiang Li:
Asynchronous Consensus of Multiple Double-Integrator Agents With Arbitrary Sampling Intervals and Communication Delays. 2301-2311 - Tao Liu, David J. Hill, Jun Zhao:
Output Synchronization of Dynamical Networks with Incrementally-Dissipative Nodes and Switching Topology. 2312-2323 - Viki Szortyka, Kuba Raczkowski, Maarten Kuijk, Piet Wambacq:
A Wideband Beamforming Lowpass Filter for 60 GHz Phased-Array Receivers. 2324-2333 - Andrea Mazzanti, Andrea Bevilacqua:
On the Phase Noise Performance of Transformer-Based CMOS Differential-Pair Harmonic Oscillators. 2334-2341 - David Seebacher, Peter Singerl, Christian Schuberth, Franz Dielacher, Yannis Papananos, Nikolaos Alexiou, Kostas Galanopoulos, Michael Ernst Gadringer, Wolfgang Bösch:
Predistortion of Digital RF PWM Signals Considering Conditional Memory. 2342-2350 - Sujan K. Manohar, L. R. Hunt, Poras T. Balsara, Dinesh K. Bhatia, Vikas V. Paduvalli:
Minimum Phase Wide Output Range Digitally Controlled SIDO Boost Converter. 2351-2360 - Yongle Wu, Lingxiao Jiao, Yuanan Liu:
Comments on "Novel Dual-Band Matching Network for Effective Design of Concurrent Dual-Band Power Amplifiers". 2361-2363
Volume 62-I, Number 10, October 2015
- Muhammad Ahmadi, Won Namgoong:
Comparator Power Minimization Analysis for SAR ADC Using Multiple Comparators. 2369-2379 - Omar Abdelfattah, Gordon W. Roberts, Ishiang Shih, Yi-Chi Shih:
An Ultra-Low-Voltage CMOS Process-Insensitive Self-Biased OTA With Rail-to-Rail Input Range. 2380-2390 - Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Naudet:
Exploiting Pipeline ADC Properties for a Reduced-Code Linearity Test Technique. 2391-2400 - Kun Zhou, Diyi Chen, Xu Zhang, Rui Zhou, Herbert Ho-Ching Iu:
Fractional-Order Three-Dimensional ∇ × n Circuit Network. 2401-2410 - Jung-Mao Lin, Ching-Yuan Yang:
A Fast-Locking All-Digital Phase-Locked Loop With Dynamic Loop Bandwidth Adjustment. 2411-2422 - Thomas Charisoulis, Douglas Frey, Miltiadis K. Hatalis:
Current Feedback Compensation Circuit for 2T1C LED Displays: Method. 2423-2433 - Li Lu, Bozorgmehr Vosooghi, Liang Dai, Changzhi Li:
A 0.7 V Relative Temperature Sensor With a Non-Calibrated $\pm 1~^{\circ}{\rm C}$ 3$\sigma$ Relative Inaccuracy. 2434-2444 - Yu-Te Liao, Shih-Chieh Huang, Fuyuan Cheng, Tsung-Heng Tsai:
A Fully-Integrated Wireless Bondwire Accelerometer With Closed-loop Readout Architecture. 2445-2453 - Gennady A. Leonov, Nikolay V. Kuznetsov, Marat V. Yuldashev, Renat V. Yuldashev:
Hold-In, Pull-In, and Lock-In Ranges of PLL Circuits: Rigorous Mathematical Definitions and Limitations of Classical Theory. 2454-2464 - Wasim Hussain, Yves Blaquière, Yvon Savaria:
An Interface for Open-Drain Bidirectional Communication in Field Programmable Interconnection Networks. 2465-2475 - Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi:
High-Performance Four-Stage CMOS OTA Suitable for Large Capacitive Loads. 2476-2484 - Javier Agustin, Marisa López-Vallejo:
An In-Depth Analysis of Ring Oscillators: Exploiting Their Configurable Duty-Cycle. 2485-2494 - Young-Ju Kim, Sang-Hye Chung, Kyung-Soo Ha, Seung-Jun Bae, Lee-Sup Kim:
A 9.6 Gb/s 0.96 mW/Gb/s Forwarded Clock Receiver With High Jitter Tolerance Using Mixing Cell Integrated Injection-Locked Oscillator. 2495-2503 - Suhas Illath Veetil, Mohamed Helaoui:
Discrete Implementation and Linearization of a New Polar Modulator-Based Mixerless Wireless Transmitter Suitable for High Reconfigurability. 2504-2511 - Wei-Cheng Sun, Wei-Hsuan Wu, Chia-Hsiang Yang, Yeong-Luh Ueng:
An Iterative Detection and Decoding Receiver for LDPC-Coded MIMO Systems. 2512-2522 - Chia-Lung Lin, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
Jointly Designed Nonbinary LDPC Convolutional Codes and Memory-Based Decoder Architecture. 2523-2532 - Wanxin Ye, Kaixue Ma, Kiat Seng Yeo, Qiong Zou:
A 65 nm CMOS Power Amplifier With Peak PAE above 18.9% From 57 to 66 GHz Using Synthesized Transformer-Based Matching Network. 2533-2543 - Jingyi Wang, Chen Xu, Jianwen Feng, Michael Z. Q. Chen, Xiaofan Wang, Yi Zhao:
Synchronization in Moving Pulse-Coupled Oscillator Networks. 2544-2554 - Ning He, Dawei Shi:
Event-Based Robust Sampled-Data Model Predictive Control: A Non-Monotonic Lyapunov Function Approach. 2555-2564 - Kai-Yu Hu, Shih-Mei Lin, Chien-Hung Tsai:
A Fixed-Frequency Quasi-${\rm V}^{2}$ Hysteretic Buck Converter With PLL-Based Two-Stage Adaptive Window Control. 2565-2573 - Elisenda Bou-Balust, Aiguo Patrick Hu, Eduard Alarcón:
Scalability Analysis of SIMO Non-Radiative Resonant Wireless Power Transfer Systems Based on Circuit Models. 2574-2583 - Zhangming Zhu, Yongyuan Li:
A Floating Buck Controlled Multi-Mode Dimmable LED Driver Using a Stacked NMOS Switch. 2584-2593 - Wen-Liang Hsue, Wei-Ching Chang:
Real Discrete Fractional Fourier, Hartley, Generalized Fourier and Generalized Hartley Transforms With Many Parameters. 2594-2605 - Fernando Chierchie, Sven Ole Aase:
Volterra Models for Digital PWM and Their Inverses. 2606-2616 - Robert Rieger:
Signal-Folding for Range-Enhanced Acquisition and Reconstruction. 2617-2625
Volume 62-I, Number 11, November 2015
- Yuan Cao, Le Zhang, Siarhei S. Zalivaka, Chip-Hong Chang, Shoushun Chen:
CMOS Image Sensor Based Physical Unclonable Function for Coherent Sensor-Level Authentication. 2629-2640 - Gianluca Giustolisi, Gaetano Palumbo:
Three-Stage Dynamic-Biased CMOS Amplifier With a Robust Optimization of the Settling Time. 2641-2651 - Dimitri Galayko, Andrii Dudka, Armine Karami, Eoghan O'Riordan, Elena Blokhina, Orla Feely, Philippe Basset:
Capacitive Energy Conversion With Circuits Implementing a Rectangular Charge-Voltage Cycle - Part 1: Analysis of the Electrical Domain. 2652-2663 - Eoghan O'Riordan, Andrii Dudka, Dimitri Galayko, Philippe Basset, Orla Feely, Elena Blokhina:
Capacitive Energy Conversion With Circuits Implementing a Rectangular Charge-Voltage Cycle Part 2: Electromechanical and Nonlinear Analysis. 2664-2673 - Gajendranath Chowdary, Shouri Chatterjee:
A 300-nW Sensitive, 50-nA DC-DC Converter for Energy Harvesting Applications. 2674-2684 - Schekeb Fateh, Philipp Schoenle, Luca Bettini, Giovanni Rovere, Luca Benini, Qiuting Huang:
A Reconfigurable 5-to-14 bit SAR ADC for Battery-Powered Medical Instrumentation. 2685-2694 - Xin Lou, Ya Jun Yu, Pramod Kumar Meher:
New Approach to the Reduction of Sign-Extension Overhead for Efficient Implementation of Multiple Constant Multiplications. 2695-2705 - Zhiting Yan, Guanghui He, Yifan Ren, Weifeng He, Jianfei Jiang, Zhigang Mao:
Design and Implementation of Flexible Dual-Mode Soft-Output MIMO Detector With Channel Preprocessing. 2706-2717 - David E. Bellasi, Luca Benini:
Energy-Efficiency Analysis of Analog and Digital Compressive Sensing in Wireless Sensors. 2718-2729 - Chunyan Wang, Zongyu Zuo, Zongli Lin, Zhengtao Ding:
Consensus Control of a Class of Lipschitz Nonlinear Systems With Input Delay. 2730-2738 - Henri Ruotsalainen, Norbert Leder, Bernhard Pichler, Holger Arthaber, Gottfried Magerl:
Equivalent Complex Baseband Model for Digital Transmitters Based on 1-bit Quadrature Pulse Encoding. 2739-2747 - Mohamed Zgaren, Mohamad Sawan:
A Low-Power Dual-Injection-Locked RF Receiver With FSK-to-OOK Conversion for Biomedical Implants. 2748-2758 - Dong Yang, Caroline Andrews, Alyosha C. Molnar:
Optimized Design of N-Phase Passive Mixer-First Receivers in Wideband Operation. 2759-2770 - Yuval Beck, Nir Eden, Shira Sandbank, Sigmond Singer, Keyue Ma Smedley:
On Loss Mechanisms of Complex Switched Capacitor Converters. 2771-2780 - Tomoharu Nagashima, Xiuqin Wei, Elisenda Bou, Eduard Alarcón, Marian K. Kazimierczuk, Hiroo Sekiya:
Analysis and Design of Loosely Inductive Coupled Wireless Power Transfer System Based on Class-E2 DC-DC Converter for Efficiency Enhancement. 2781-2791
Volume 62-I, Number 12, December 2015
- Shanthi Pavan:
Outgoing Editorial. 2793-2794 - Pekka Keränen, Juha Kostamovaara:
A Wide Range, 4.2 ps(rms) Precision CMOS TDC With Cyclic Interpolators Based on Switched-Frequency Ring Oscillators. 2795-2805 - Shanshan Dai, Ronald W. Knepper, Mark N. Horenstein:
A 300-V LDMOS Analog-Multiplexed Driver for MEMS Devices. 2806-2816 - Soon-Won Kwon, Joon-Yeong Lee, Jinhee Lee, Kwangseok Han, Taeho Kim, Sangeun Lee, Jeong-Sup Lee, Taehun Yoon, Hyosup Won, Jinho Park, Hyeon-Min Bae:
An Automatic Loop Gain Control Algorithm for Bang-Bang CDRs. 2817-2828 - Mohammad Saeed Sarafraz, Mohammad Saleh Tavazoei:
Realizability of Fractional-Order Impedances by Passive Electrical Networks Composed of a Fractional Capacitor and RLC Components. 2829-2835 - Pramod Kumar Meher, Basant Kumar Mohanty, Sujit Kumar Patel, Soumya Ganguly, Thambipillai Srikanthan:
Efficient VLSI Architecture for Decimation-in-Time Fast Fourier Transform of Real-Valued Data. 2836-2845 - Chiou-Yng Lee, Pramod Kumar Meher:
Area-Efficient Subquadratic Space-Complexity Digit-Serial Multiplier for Type-II Optimal Normal Basis of GF(2m) Using Symmetric TMVP and Block Recombination Techniques. 2846-2855 - Robert L. Shuler:
Porting and Scaling Strategies for Nanoscale CMOS RHBD. 2856-2863 - Hao Wang:
A New Separable Two-dimensional Finite Impulse Response Filter Design With Sparse Coefficients. 2864-2873 - Tianqi Hong, Francisco de León:
Lissajous Curve Methods for the Identification of Nonlinear Circuits: Calculation of a Physical Consistent Reactive Power. 2874-2885 - Marco Crepaldi, Matteo Stoppa, Paolo Motto Ros, Danilo Demarchi:
An Analog-Mode Impulse Radio System for Ultra-Low Power Short-Range Audio Streaming. 2886-2897 - Taesong Hwang, Kamran Azadet, Ross S. Wilson, Jenshan Lin:
Nonlinearity Modeling of a Chireix Outphasing Power Amplifier. 2898-2907 - Vinaya M. M., Roy P. Paily, Anil Mahanta:
A New PVT Compensation Technique Based on Current Comparison for Low-Voltage, Near Sub-Threshold LNA. 2908-2919 - Injae Yoo, Bongjin Kim, In-Cheol Park:
Reverse Rate Matching for Low-Power LTE-Advanced Turbo Decoders. 2920-2928 - Pei-Yun Tsai, Po-Cheng Lo, Fong-Jay Shih, Wen-Ji Jau, Meng-Yuan Huang, Zheng-Yu Huang:
A 4×4 MIMO-OFDM Baseband Receiver With 160 MHz Bandwidth for Indoor Gigabit Wireless Communications. 2929-2939 - Nunzio Spina, Vincenzo Fiore, Pierpaolo Lombardo, Egidio Ragonese, Giuseppe Palmisano:
Current-Reuse Transformer-Coupled Oscillators With Output Power Combining for Galvanically Isolated Power Transfer Systems. 2940-2948
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-10-30 00:41 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
