default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDIEEE Transactions on Circuits and Systems - Part I: Regular Papers, Volume 62-I
Volume 62-I, Number 1, January 2015
- Kin Keung Lee, Tor Sverre Lande
, Philipp Dominik Häfliger:
A Sub-µW Bandgap Reference Circuit With an Inherent Curvature-Compensation Property. 1-9 - Yung-Hui Chung, Meng-Hsuan Wu, Hung-Sung Li:
A 12-bit 8.47-fJ/Conversion-Step Capacitor-Swapping SAR ADC in 110-nm CMOS. 10-18 - Haoran Yu, Kamal El-Sankary, Ezz I. El-Masry:
Distortion Analysis Using Volterra Series and Linearization Technique of Nano-Scale Bulk-Driven CMOS RF Amplifier. 19-28 - Dong Wu, Cencen Gao, Hui Liu, Nan Xie:
A Low Power Double-Sampling Extended Counting ADC With Class-AB OTA for Sensor Arrays. 29-38 - Behnam Sedighi, Xiaobo Sharon Hu, Huichu Liu, Joseph J. Nahas, Michael T. Niemier:
Analog Circuit Design Using Tunnel-FETs. 39-48 - John A. McNeill, Rabeeh Majidi, Jianping Gong:
"Split ADC" Background Linearization of VCO-Based ADCs. 49-58 - Chao-Chang Chiu, Po-Hsien Huang, Moris Lin, Ke-Horng Chen, Ying-Hsi Lin, Tsung-Yen Tsai, Chao-Cheng Lee:
A 0.6 V Resistance-Locked Loop Embedded Digital Low Dropout Regulator in 40 nm CMOS With 80.5% Power Supply Rejection Improvement. 59-69 - Jin-Yi Lin, Chih-Cheng Hsieh:
A 0.3 V 10-bit 1.17 f SAR ADC With Merge and Split Switching in 90 nm CMOS. 70-79 - Inhee Lee, Gunhee Han, Youngcheol Chae:
A 2 mW, 50 dB DR, 10 MHz BW 5 × Interleaved Bandpass Delta-Sigma Modulator at 50 MHz IF. 80-89 - Chun-Wei Hsu, Karthik Tripurari, Shih-An Yu, Peter R. Kinget:
A Sub-Sampling-Assisted Phase-Frequency Detector for Low-Noise PLLs With Robust Operation Under Supply Interference. 90-99 - Jaehyuk Choi, Jungsoon Shin, Byongmin Kang:
An Architecture With Pipelined Background Suppression and In-Situ Noise Cancelling for 2D/3D CMOS Image Sensor. 100-109 - Jiafeng Xie, Pramod Kumar Meher, Zhi-Hong Mao:
High-Throughput Finite Field Multipliers Using Redundant Basis for FPGA and ASIC Implementations. 110-119 - Chao Sun, Asuka Arakawa, Ken Takeuchi:
SEA-SSD: A Storage Engine Assisted SSD With Application-Coupled Simulation Platform. 120-129 - Nerhun Yildiz, Evren Cesur, Kamer Kayaer, Vedat Tavsanoglu, Murathan Alpay:
Architecture of a Fully Pipelined Real-Time Cellular Neural Network Emulator. 130-138 - Chao Wang, Jun Zhou, Roshan Weerasekera, Bin Zhao, Xin Liu, Philippe Royannez, Minkyu Je:
BIST Methodology, Architecture and Circuits for Pre-Bond TSV Testing in 3D Stacking IC Systems. 139-148 - Moshe Avital, Hadar Dagan, Itamar Levi, Osnat Keren, Alexander Fish:
DPA-Secured Quasi-Adiabatic Logic (SQAL) for Low-Power Passive RFID Tags Employing S-Boxes. 149-156 - Donald Donglong Chen, Nele Mentens, Frederik Vercauteren, Sujoy Sinha Roy, Ray C. C. Cheung, Derek Chi-Wai Pao, Ingrid Verbauwhede:
High-Speed Polynomial Multiplication Architecture for Ring-LWE and SHE Cryptosystems. 157-166 - Hisato Fujisaka, Takeshi Kamio, Chang-Jun Ahn, Masahiro Sakamoto, Kazuhisa Haeiwa:
A Sigma-Delta Domain Lowpass Wave Filter. 167-176 - Jesus Omar Lacruz, Francisco Garcia-Herrero, Javier Valls-Coquillat, David Declercq:
One Minimum Only Trellis Decoder for Non-Binary Low-Density Parity-Check Codes. 177-184 - Kang-Yi Fan, Pei-Yun Tsai:
An RLS Tracking and Iterative Detection Engine for Mobile MIMO-OFDM Systems. 185-194 - Aimin Jiang, Hon Keung Kwan, Yanping Zhu, Xiaofeng Liu, Ning Xu, Yibin Tang:
Design of Sparse FIR Filters With Joint Optimization of Sparsity and Filter Order. 195-204 - Gourav Saha, Ramkrishna Pasumarthy, Prathamesh Khatavkar:
Towards Analog Memristive Controllers. 205-214 - Shyam Prasad Adhikari, Hyongsuk Kim, Ram Kaji Budhathoki, Changju Yang, Leon O. Chua:
A Circuit-Based Learning Architecture for Multilayer Neural Networks With Memristor Bridge Synapses. 215-223 - Jiajia Chen, Chip-Hong Chang, Feng Feng, Weiao Ding, Jiatao Ding:
Novel Design Algorithm for Low Complexity Programmable FIR Filters Based on Extended Double Base Number System. 224-233 - Kim B. Ostman, Mikko Englund, Olli Viitala, Mikko Kaltiokallio, Kari Stadius, Kimmo Koli, Jussi Ryynänen:
Analysis and Design of N-Path Filter Offset Tuning in a 0.7-2.7-GHz Receiver Front-End. 234-243 - Soo-Hwan Shin, Soon-Jae Kweon, Seong-Hun Jo, Yong-Chang Choi, Sangyoub Lee, Hyung-Joun Yoo:
A 0.7-MHz-10-MHz CT+DT Hybrid Baseband Chain With Improved Passband Flatness for LTE Application. 244-253 - Ahmed Farouk Aref, Thomas M. Hone, Renato Negra:
A Study of the Impact of Delay Mismatch on Linearity of Outphasing Transmitters. 254-262 - Lammert Duipmans, Remko E. Struiksma, Eric A. M. Klumperink, Bram Nauta, Frank E. van Vliet:
Analysis of the Signal Transfer and Folding in N-Path Filters With a Series Inductance. 263-272 - Amin Ojani, Behzad Mesgarzadeh, Atila Alvandpour:
Monte Carlo-Free Prediction of Spurious Performance for ECDLL-Based Synthesizers. 273-282 - Basant Kumar Mohanty:
Novel Block-Formulation and Area-Delay-Efficient Reconfigurable Interpolation Filter Architecture for Multi-Standard SDR Applications. 283-291 - Chunshu Li, Min Li, Marian Verhelst, André Bourdoux, Liesbet Van der Perre, Sofie Pollin:
On the General Mathematical Framework, Calibration/Compensation Method, and Applications of Non-Ideal Software Defined Harmonics Rejection Transceivers. 292-301 - Hoang Nguyen, Johnson I. Agbinya, John Devlin:
FPGA-Based Implementation of Multiple Modes in Near Field Inductive Communication Using Frequency Splitting and MIMO Configuration. 302-310 - Yasuhiro Sugimoto, Toru Sai, Kei Watanabe, Mikio Abe:
Feedback Loop Analysis and Optimized Compensation Slope of the Current-Mode Buck DC-DC Converter in DCM. 311-319 - Weiguo Lu, Shuang Lang, Luowei Zhou, Herbert Ho-Ching Iu, Tyrone Fernando:
Improvement of Stability and Power Factor in PCM Controlled Boost PFC Converter With Hybrid Dynamic Compensation. 320-328 - Mohammad Saleh Tavazoei:
Comments on "Chaotic Characteristics Analysis and Circuit Implementation for a Fractional-Order System". 329-332 - Wan Mariam Wan Muda, Victor Sreeram, Ha Binh Minh, Abdul Ghafoor:
Comments on "Model-Order Reduction Using Variational Balanced Truncation With Spectral Shaping". 333-335
Volume 62-I, Number 2, February 2015
- Siamak Hafizi-Moori, Edmond Cretu:
Weakly-Coupled Resonators in Capacitive Readout Circuits. 337-346 - Samira Bashiri, Sadok Aouini, Naim Ben-Hamida, Calvin Plett:
Analysis and Modeling of the Phase Detector Hysteresis in Bang-Bang PLLs. 347-355 - Lei Sun, Bing Li, Alex K. Y. Wong, Wai Tung Ng, Kong-Pang Pun:
A Charge Recycling SAR ADC With a LSB-Down Switching Scheme. 356-365 - Yonghong Tao, Yong Lian:
A 0.8-V, 1-MS/s, 10-bit SAR ADC for Multi-Channel Neural Recording. 366-375 - Xin Meng, Yi Zhang, Tao He, Gabor C. Temes:
Low-Distortion Wideband Delta-Sigma ADCs With Shifted Loop Delays. 376-384 - Inna Vaisband, Mahmoud Saadat, Boris Murmann:
A Closed-Loop Reconfigurable Switched-Capacitor DC-DC Converter for Sub-mW Energy Harvesting Applications. 385-394 - Jinn-Shyan Wang, Chun-Yuan Cheng:
An All-Digital Delay-Locked Loop Using an In-Time Phase Maintenance Scheme for Low-Jitter Gigahertz Operations. 395-404 - Po-Hung Chen, Philex Ming-Yan Fan:
An 83.4% Peak Efficiency Single-Inductor Multiple-Output Based Adaptive Gate Biasing DC-DC Converter for Thermoelectric Energy Harvesting. 405-412 - Michele Caruso, Matteo Bassi, Andrea Bevilacqua, Andrea Neviani:
A 2-16 GHz 65 nm CMOS Stepped-Frequency Radar Transmitter With Harmonic Rejection for High-Resolution Medical Imaging Applications. 413-422 - Frédéric Broydé, Evelyne Clavelier:
Some Properties of Multiple-Antenna-Port and Multiple-User-Port Antenna Tuners. 423-432 - Ettore Lorenzo Firrao, Anne-Johan Annema, Frank E. van Vliet, Bram Nauta:
On the Minimum Number of States for Switchable Matching Networks. 433-440 - Bo Wang, Truc Quynh Nguyen, Anh-Tuan Do, Jun Zhou, Minkyu Je, Tony Tae-Hyoung Kim:
Design of an Ultra-low Voltage 9T SRAM With Equalized Bitline Leakage and CAM-Assisted Energy Efficiency Improvement. 441-448 - Maher Jridi, Ayman Alfalou, Pramod Kumar Meher:
A Generalized Algorithm and Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT. 449-457 - Mahsa Shoaran, Armin Tajalli, Massimo Alioto, Alexandre Schmid, Yusuf Leblebici:
Analysis and Characterization of Variability in Subthreshold Source-Coupled Logic Circuits. 458-467 - Insup Shin, Jae-Joon Kim, Youngsoo Shin:
Aggressive Voltage Scaling Through Fast Correction of Multiple Errors With Seamless Pipeline Operation. 468-477 - Kenichiro Cho, Takaya Miyano:
Chaotic Cryptography Using Augmented Lorenz Equations Aided by Quantum Key Distribution. 478-487 - Zdenek Biolek, Dalibor Biolek, Viera Biolková:
(Co)content in Circuits With Memristive Elements. 488-496 - Przemyslaw Mroszczyk, Piotr Dudek:
Trigger-Wave Asynchronous Cellular Logic Array for Fast Binary Image Processing. 497-506 - Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
A 7.92 Gb/s 437.2 mW Stochastic LDPC Decoder Chip for IEEE 802.15.3c Applications. 507-516 - Shahaboddin Moazzeni, Mohamad Sawan, Glenn E. R. Cowan:
An Ultra-Low-Power Energy-Efficient Dual-Mode Wake-Up Receiver. 517-526 - Tanbir Haque, Rabia Tugce Yazicigil, Kyle Jung-Lin Pan, John Wright, Peter R. Kinget:
Theory and Design of a Quadrature Analog-to-Information Converter for Energy-Efficient Wideband Spectrum Sensing. 527-535 - Ankush Goel, Behnam Analui, Hossein Hashemi:
Tunable Duplexer With Passive Feed-Forward Cancellation to Improve the RX-TX Isolation. 536-544 - Wei-Chang Liu, Ting-Chen Wei, Ya-Shiue Huang, Ching-Da Chan, Shyh-Jye Jou:
All-Digital Synchronization for SC/OFDM Mode of IEEE 802.15.3c and IEEE 802.11ad. 545-553 - Qiong Zou, Kaixue Ma, Kiat Seng Yeo:
A Low Phase Noise and Wide Tuning Range Millimeter-Wave VCO Using Switchable Coupled VCO-Cores. 554-563 - Joakim Osth, Magnus Karlsson, Adriana Serban, Shaofang Gong:
A Comparative Study of Single-Ended vs. Differential Six-Port Modulators for Wireless Communications. 564-570 - Maryam Jouzdani, Mohammad Mojtaba Ebrahimi, Karun Rawat, Mohamed Helaoui, Fadhel M. Ghannouchi:
Envelope Tracked Pulse Gate Modulated GaN HEMT Power Amplifier for Wireless Transmitters. 571-579 - Won Namgoong:
Adaptive and Robust Digital Harmonic-Reject Mixer With Optimized Local Oscillator Spacing. 580-589 - Juha Yli-Kaakinen, Vesa Lehtinen, Markku Renfors:
Multirate Charge-Domain Filter Design for RF-Sampling Multi-Standard Receiver. 590-599 - Chang-Jin Jeong, Yang Sun, Seok-Kyun Han, Sang-Gug Lee:
A 2.2 mW, 40 dB Automatic Gain Controllable Low Noise Amplifier for FM Receiver. 600-606 - Fabio Padovan, Marc Tiebout, Koen L. R. Mertens, Andrea Bevilacqua, Andrea Neviani:
Design of Low-Noise K-Band SiGe Bipolar VCOs: Theory and Implementation. 607-615
Volume 62-I, Number 3, March 2015
- Xing Li, Chi-Ying Tsui, Wing-Hung Ki:
Power Management Analysis of Inductively-Powered Implants with 1X/2X Reconfigurable Rectifier. 617-624 - Marius Neag, Raul Onet, István Kovács, Paul Martari:
Comparative Analysis of Simulation-Based Methods for Deriving the Phase- and Gain-Margins of Feedback Circuits With Op-Amps. 625-634 - Yongsun Lee, Mina Kim, Taeho Seong, Jaehyouk Choi:
A Low Phase Noise Injection-Locked Programmable Reference Clock Multiplier With a Two-Phase PVT-Calibrator for ΔΣ PLLs. 635-644 - Achille Donida, Remy Cellier, Angelo Nagari, Piero Malcovati, Andrea Baschirotto:
A 40-nm CMOS, 1.1-V, 101-dB Dynamic-Range, 1.7-mW Continuous-Time ΣΔ ADC for a Digital Closed-Loop Class-D Amplifier. 645-653 - Sudipta Sarkar, Yuan Zhou, Brian Elies, Yun Chiu:
PN-Assisted Deterministic Digital Background Calibration of Multistage Split-Pipelined ADC. 654-661 - Quanzhen Duan, Jeongjin Roh:
A 1.2-V 4.2- ppm°C High-Order Curvature-Compensated CMOS Bandgap Reference. 662-670 - Yao Liu, Reza Lotfi, Yongchang Hu, Wouter A. Serdijn:
A Comparative Analysis of Phase-Domain ADC and Amplitude-Domain IQ ADC. 671-679 - Anders Jakobsson, Adriana Serban, Shaofang Gong:
Implementation of Quantized-State System Models for a PLL Loop Filter Using Verilog-AMS. 680-688 - Zhangming Zhu, Zheng Qiu, Maliang Liu, Ruixue Ding:
A 6-to-10-Bit 0.5 V-to-0.9 V Reconfigurable 2 MS/s Power Scalable SAR ADC in 0.18 µm CMOS. 689-696 - Jun Zhou, Chao Wang, Xin Liu, Xin Zhang, Minkyu Je:
An Ultra-Low Voltage Level Shifter Using Revised Wilson Current Mirror for Fast and Energy-Efficient Wide-Range Voltage Conversion from Sub-Threshold to I/O Voltage. 697-706 - Yan Lu, Yipeng Wang, Quan Pan, Wing-Hung Ki, C. Patrick Yue:
A Fully-Integrated Low-Dropout Regulator With Full-Spectrum Power Supply Rejection. 707-716 - Ahmed Ashry, Diomadson Belfort, Hassan Aboushady:
Phase Noise Effect on Sine-Shaped Feedback DACs Used in Continuous-Time ΣΔ ADCs. 717-724 - Mark E. Halpern, David C. Ng:
Optimal Tuning of Inductive Wireless Power Links: Limits of Performance. 725-732 - Chenxin Zhang, Liang Liu, Dejan Markovic, Viktor Öwall:
A Heterogeneous Reconfigurable Cell Array for MIMO Signal Processing. 733-742 - Ming-Chiuan Su, Wei-Zen Chen, Pei-Si Wu, Yu-Hsian Chen, Chao-Cheng Lee, Shyh-Jye Jou:
A 10-Gb/s, 1.24 pJ/bit, Burst-Mode Clock and Data Recovery With Jitter Suppression. 743-751 - Chua-Chin Wang, Chih-Lin Chen, Zong-You Hou, Yi Hu, Jam-Wem Lee, Wan-Yen Lin, Yi-Feng Chang, Chia-Wei Hsu, Ming-Hsiang Song:
A 60 V Tolerance Transceiver With ESD Protection for FlexRay-Based Communication Systems. 752-760 - Katayoun Neshatpour, Mahdi Shabany, P. Glenn Gulak:
A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors. 761-770 - Shuhei Tanakamaru, Yuta Kitamura, Senju Yamazaki, Tsukasa Tokutomi, Ken Takeuchi:
Highly Reliable Coding Methods for Emerging Applications: Archive and Enterprise Solid-State Drives (SSDs). 771-780 - Taeho Seong, Jae Joon Kim, Jaehyouk Choi:
Analysis and Design of a Core-Size-Scalable Low Phase Noise LC-VCO for Multi-Standard Cellular Transceivers. 781-790 - Pere Palà-Schönwälder, Jordi Bonet-Dalmau, Alexis Lopez-Riera, F. Xavier Moncunill-Geniz, Francisco del Águìla López, M. Rosa Giralt-Mas:
Superregenerative Reception of Narrowband FSK Modulations. 791-798 - Xinmin Yu, Hooman Rashtian, Shahriar Mirabbasi, Partha Pratim Pande, Deuk Hyoun Heo:
An 18.7-Gb/s 60-GHz OOK Demodulator in 65-nm CMOS for Wireless Network-on-Chip. 799-806 - Shlomo Greenberg, Joseph Rabinowicz, Erez Manor:
Selective State Retention Power Gating Based on Formal Verification. 807-815 - Seongbo Shim, Jae Wook Lee, Youngsoo Shin:
An Analytical Approach to Thermal Design and Optimization With a Temperature-Dependent Power Model. 816-824 - Zhaomeng Cheng, Hai-Tao Zhang, Ming-Can Fan, Guanrong Chen:
Distributed Consensus of Multi-Agent Systems With Input Constraints: A Model Predictive Control Approach. 825-834 - Massimo Alioto, Elio Consoli, Gaetano Palumbo:
Variations in Nanometer CMOS Flip-Flops: Part II - Energy Variability and Impact of Other Sources of Variations. 835-843 - Shuhei Tanakamaru, Hiroki Yamazawa, Tsukasa Tokutomi, Sheyang Ning, Ken Takeuchi:
Design Methodology for Highly Reliable, High Performance ReRAM and 3-Bit/Cell MLC NAND Flash Solid-State Storage. 844-853 - Chiou-Yng Lee, Pramod Kumar Meher:
Efficient Subquadratic Space Complexity Architectures for Parallel MPB Single- and Double-Multiplications for All Trinomials Using Toeplitz Matrix-Vector Product Decomposition. 854-862 - Xin Lou, Ya Jun Yu, Pramod Kumar Meher:
Fine-Grained Critical Path Analysis and Optimization for Area-Time Efficient Realization of Multiple Constant Multiplications. 863-872 - María del Carmen Pérez, Rodrigo Garcia, Álvaro Hernández, Ana Jiménez, Cristina Diego, Jesús Ureña:
SoC-Based Architecture for an Ultrasonic Phased Array With Encoded Transmissions. 873-880 - Jiafeng Xie, Pramod Kumar Meher, Zhi-Hong Mao:
Low-Latency High-Throughput Systolic Multipliers Over GF(2m) for NIST Recommended Pentanomials. 881-890 - Maheshwar Pd. Sah, Changju Yang, Hyongsuk Kim, Bharathwaj Muthuswamy, Jovan Jevtic, Leon O. Chua:
A Generic Model of Memristors With Parasitic Components. 891-898 - Xiang Li, Pengchun Rao:
Synchronizing a Weighted and Weakly-Connected Kuramoto-Oscillator Digraph With a Pacemaker. 899-905 - Mika Laiho, Jennifer O. Hasler, Jiantao Zhou, Chao Du, Wei Lu, Eero Lehtonen, Jussi H. Poikonen:
FPAA/Memristor Hybrid Computing Infrastructure. 906-915 - Xin Zhang, Xinbo Ruan, Chi K. Tse:
Impedance-Based Local Stability Criterion for DC Distributed Power Systems. 916-925
Volume 62-I, Number 4, April 2015
- Ahmet Gokcen Mahmutoglu, Alper Demir:
Analysis of Low-Frequency Noise in Switched MOSFET Circuits: Revisited and Clarified. 929-937 - Shunta Iguchi, Pyungwoo Yeon, Hiroshi Fuketa, Koichi Ishida, Takayasu Sakurai, Makoto Takamiya:
Wireless Power Transfer With Zero-Phase-Difference Capacitance Control. 938-947 - Zohaib Hameed, Kambiz Moez:
A 3.2 V -15 dBm Adaptive Threshold-Voltage Compensated RF Energy Harvester in 130 nm CMOS. 948-956 - Thomas Souvignet, Bruno Allard, Xuefang Lin-Shi:
Sampled-Data Modeling of Switched- Capacitor Voltage Regulator With Frequency-Modulation Control. 957-966 - Lucas G. de Carli, Yuri Juppa, Adilson J. Cardoso, Carlos Galup-Montoro, Márcio C. Schneider:
Maximizing the Power Conversion Efficiency of Ultra-Low-Voltage CMOS Multi-Stage Rectifiers. 967-975 - Yao Zhu, Yuanjin Zheng, Yuan Gao, I. Made Darmayuda, Chengliang Sun, Minkyu Je, Alex Yuandong Gu:
An Energy Autonomous 400 MHz Active Wireless SAW Temperature Sensor Powered by Vibration Energy Harvesting. 976-985 - Kai Wang, Michael Z. Q. Chen:
Minimal Realizations of Three-Port Resistive Networks. 986-994 - Ding Nie, Bertrand M. Hochwald:
Broadband Matching Bounds for Coupled Loads. 995-1004 - Xinwang Zhang, Baoyong Chi, Zhihua Wang:
A 0.1-1.5 GHz Harmonic Rejection Receiver Front-End With Phase Ambiguity Correction, Vector Gain Calibration and Blocker-Resilient TIA. 1005-1014 - Peng Chen, Songbai He:
Investigation of Inverse Class-E Power Amplifier at Sub-Nominal Condition for Any Duty Ratio. 1015-1024 - Chak-Fong Cheang, Ka-Fai Un, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins:
A Combinatorial Impairment-Compensation Digital Predistorter for a Sub-GHz IEEE 802.11af-WLAN CMOS Transmitter Covering a 10x-Wide RF Bandwidth. 1025-1032 - Seyed Mohammadreza Fatemi, Mohammad Sharifkhani, Ali Fotowat-Ahmady:
A Unified Solution for Super-Regenerative Systems With Application to Correlator-Based UWB Transceivers. 1033-1041 - Fanta Chen, Jen-Ming Wu, Mau-Chung Frank Chang:
40-Gb/s 0.7-V 2: 1 MUX and 1: 2 DEMUX with Transformer-Coupled Technique for SerDes Interface. 1042-1051 - Thomas A. F. Theunisse, Jun Chai, Ricardo G. Sanfelice, W. P. M. H. Heemels:
Robust Global Stabilization of the DC-DC Boost Converter via Hybrid Control. 1052-1061