"A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line ..."

Nan-Chun Lien et al. (2014)

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DOI: 10.1109/TCSI.2014.2336531

access: closed

type: Journal Article

metadata version: 2020-05-22

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Nan-Chun Lien, Li-Wei Chu, Chien-Hen Chen, Hao-I Yang, Ming-Hsien Tu, Paul-Sen Kan, Yong-Jyun Hu, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang:
A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(12): 3416-3425 (2014)

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