"Timing Challenges for Very Deep Sub-Micron (VDSM) IC."

Ichiang Lin, Chien-In Henry Chen (2002)

> Home

Details and statistics

DOI: 10.1080/1065514021000012183

access: open

type: Journal Article

metadata version: 2023-05-08

- view
  - electronic edition via DOI (open access)
  authority control:
- export record
  dblp key:
  - journals/vlsi/LinC02
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/vlsi/LinC02
Ichiang Lin, Chien-In Henry Chen:
Timing Challenges for Very Deep Sub-Micron (VDSM) IC. VLSI Design 15(3): 557-562 (2002)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.