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@article{DBLP:journals/vlsi/AreibiV00,
author = {Shawki Areibi and
Anthony Vannelli},
title = {Tabu Search: {A} Meta Heuristic for Netlist Partitioning},
journal = {{VLSI} Design},
volume = {11},
number = {3},
pages = {259--283},
year = {2000},
url = {https://doi.org/10.1155/2000/62159},
doi = {10.1155/2000/62159},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/AreibiV00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/BazylevychMR00,
author = {Roman P. Bazylevych and
R. A. Melnyk and
O. G. Rybak},
title = {Circuit Partitioning for FPGAs by the Optimal Circuit Reduction Method},
journal = {{VLSI} Design},
volume = {11},
number = {3},
pages = {237--248},
year = {2000},
url = {https://doi.org/10.1155/2000/58485},
doi = {10.1155/2000/58485},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/BazylevychMR00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/CaldwellKM00,
author = {Andrew E. Caldwell and
Andrew B. Kahng and
Igor L. Markov},
title = {Iterative Partitioning with Varying Node Weights},
journal = {{VLSI} Design},
volume = {11},
number = {3},
pages = {249--258},
year = {2000},
url = {https://doi.org/10.1155/2000/15862},
doi = {10.1155/2000/15862},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/CaldwellKM00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/ChenC00,
author = {Sao{-}Jie Chen and
Chung{-}Kuan Cheng},
title = {Tutorial on {VLSI} Partitioning},
journal = {{VLSI} Design},
volume = {11},
number = {3},
pages = {175--218},
year = {2000},
url = {https://doi.org/10.1155/2000/53913},
doi = {10.1155/2000/53913},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/ChenC00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/ChenZ00,
author = {Chien{-}In Henry Chen and
Yingjie Zhou},
title = {Configurable 2-D Linear Feedback Shift Registers for {VLSI} Built-in
Self-test Designs},
journal = {{VLSI} Design},
volume = {11},
number = {2},
pages = {149--159},
year = {2000},
url = {https://doi.org/10.1155/2000/60904},
doi = {10.1155/2000/60904},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/ChenZ00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/Dempster00,
author = {Andrew G. Dempster},
title = {Graphical Design Techniques for Fixed-point Multiplication},
journal = {{VLSI} Design},
volume = {11},
number = {4},
pages = {363--379},
year = {2000},
url = {https://doi.org/10.1155/2000/30196},
doi = {10.1155/2000/30196},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/Dempster00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/DmitrievSSGMM00,
author = {Alexej Dmitriev and
Valerij V. Saposhnikov and
Vladimir V. Saposhnikov and
Michael G{\"{o}}ssel and
V. Moshanin and
Andrej A. Morosov},
title = {New Self-dual Circuits for Error Detection and Testing},
journal = {{VLSI} Design},
volume = {11},
number = {1},
pages = {1--21},
year = {2000},
url = {https://doi.org/10.1155/2000/84720},
doi = {10.1155/2000/84720},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/DmitrievSSGMM00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/FalkowskiC00,
author = {Bogdan J. Falkowski and
Chip{-}Hong Chang},
title = {Minimization of \emph{k}-Variable-Mixed-Polarity Reed-Muller Expansions},
journal = {{VLSI} Design},
volume = {11},
number = {4},
pages = {311--320},
year = {2000},
url = {https://doi.org/10.1155/2000/64575},
doi = {10.1155/2000/64575},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/FalkowskiC00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/FalkowskiS00,
author = {Bogdan J. Falkowski and
Radomir S. Stankovic},
title = {Spectral Interpretation and Applications of Decision Diagrams},
journal = {{VLSI} Design},
volume = {11},
number = {2},
pages = {85--105},
year = {2000},
url = {https://doi.org/10.1155/2000/95282},
doi = {10.1155/2000/95282},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/FalkowskiS00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/HatirnazGL00,
author = {Ilhan Hatirnaz and
Frank K. G{\"{u}}rkaynak and
Yusuf Leblebici},
title = {A Modular and Scalable Architecture for the Realization of High-speed
Programmable Rank Order Filters Using Threshold Logic},
journal = {{VLSI} Design},
volume = {11},
number = {2},
pages = {115--128},
year = {2000},
url = {https://doi.org/10.1155/2000/98945},
doi = {10.1155/2000/98945},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/HatirnazGL00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/KarypisK00,
author = {George Karypis and
Vipin Kumar},
title = {Multilevel \emph{k}-way Hypergraph Partitioning},
journal = {{VLSI} Design},
volume = {11},
number = {3},
pages = {285--300},
year = {2000},
url = {https://doi.org/10.1155/2000/19436},
doi = {10.1155/2000/19436},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/KarypisK00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/KavousianosNS00,
author = {Xrysovalantis Kavousianos and
Dimitris Nikolos and
G. Sidiropoulos},
title = {Novel Single and Double Output {TSC} {CMOS} Checkers for \emph{m}-out-of-\emph{n}
Codes},
journal = {{VLSI} Design},
volume = {11},
number = {1},
pages = {35--45},
year = {2000},
url = {https://doi.org/10.1155/2000/89292},
doi = {10.1155/2000/89292},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/KavousianosNS00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/KimC00,
author = {Dong{-}Wook Kim and
Tae{-}Yong Choi},
title = {Delay Time Estimation Model for Large Digital {CMOS} Circuits},
journal = {{VLSI} Design},
volume = {11},
number = {2},
pages = {161--173},
year = {2000},
url = {https://doi.org/10.1155/2000/18189},
doi = {10.1155/2000/18189},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/KimC00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/Lala00,
author = {Parag K. Lala},
title = {Guest Editorial},
journal = {{VLSI} Design},
volume = {11},
number = {1},
year = {2000},
url = {https://doi.org/10.1155/2000/38343},
doi = {10.1155/2000/38343},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/Lala00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/LiuZW00,
author = {Huiqun Liu and
Kai Zhu and
D. F. Wong},
title = {{FPGA} Partitioning with Complex Resource Constraints},
journal = {{VLSI} Design},
volume = {11},
number = {3},
pages = {219--235},
year = {2000},
url = {https://doi.org/10.1155/2000/12198},
doi = {10.1155/2000/12198},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/LiuZW00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/Lopez-MartinC00,
author = {Antonio J. L{\'{o}}pez{-}Mart{\'{\i}}n and
Alfonso Carlosena},
title = {Design of MOS-translinear Multiplier/Dividers in Analog {VLSI}},
journal = {{VLSI} Design},
volume = {11},
number = {4},
pages = {321--329},
year = {2000},
url = {https://doi.org/10.1155/2000/21852},
doi = {10.1155/2000/21852},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/Lopez-MartinC00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/MasupeA00,
author = {S. Masupe and
Tughrul Arslan},
title = {Low Power {VLSI} Implementation of the {DCT} on Single Multiplier
{DSP} Processors},
journal = {{VLSI} Design},
volume = {11},
number = {4},
pages = {397--403},
year = {2000},
url = {https://doi.org/10.1155/2000/34760},
doi = {10.1155/2000/34760},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/MasupeA00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/MatrosovaLO00,
author = {Anzhela Yu. Matrosova and
Ilya Levin and
Sergey Ostanin},
title = {Self-checking Synchronous {FSM} Network Design with Low Overhead},
journal = {{VLSI} Design},
volume = {11},
number = {1},
pages = {47--58},
year = {2000},
url = {https://doi.org/10.1155/2000/46578},
doi = {10.1155/2000/46578},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/MatrosovaLO00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/MetraFR00,
author = {Cecilia Metra and
Michele Favalli and
Bruno Ricc{\`{o}}},
title = {Signal Coding and {CMOS} Gates for Combinational Functional Blocks
of Very Deep Submicron Self-checking Circuits},
journal = {{VLSI} Design},
volume = {11},
number = {1},
pages = {23--34},
year = {2000},
url = {https://doi.org/10.1155/2000/42016},
doi = {10.1155/2000/42016},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/MetraFR00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/ParkKL00,
author = {Chaeryung Park and
Taewhan Kim and
C. L. Liu},
title = {An Integrated Approach to Data Path Synthesis for Behavioral-level
Power Optimization},
journal = {{VLSI} Design},
volume = {11},
number = {4},
pages = {381--396},
year = {2000},
url = {https://doi.org/10.1155/2000/76384},
doi = {10.1155/2000/76384},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/ParkKL00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/PatnaikG00,
author = {L. M. Patnaik and
Satrajit Gupta},
title = {Exact Output Response Computation of {RC} Interconnects Under General
Polynomial Input Waveforms},
journal = {{VLSI} Design},
volume = {11},
number = {2},
pages = {75--84},
year = {2000},
url = {https://doi.org/10.1155/2000/48985},
doi = {10.1155/2000/48985},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/PatnaikG00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/Rodriguez-Villegas00,
author = {Esther Rodr{\'{\i}}guez{-}Villegas and
Maria J. Avedillo and
Jos{\'{e}} M. Quintana and
Gloria Huertas and
Adoraci{\'{o}}n Rueda},
title = {{\(\nu\)}MOS-based Sorter for Arithmetic Applications},
journal = {{VLSI} Design},
volume = {11},
number = {2},
pages = {129--136},
year = {2000},
url = {https://doi.org/10.1155/2000/57240},
doi = {10.1155/2000/57240},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/Rodriguez-Villegas00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/RomanGG00,
author = {D. Torres Roman and
J. Gonzalez and
M. Guzman},
title = {A New Bus Assignment Algorithm for a Shared Bus Switch Fabric},
journal = {{VLSI} Design},
volume = {11},
number = {4},
pages = {339--351},
year = {2000},
url = {https://doi.org/10.1155/2000/26425},
doi = {10.1155/2000/26425},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/RomanGG00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/RomanLG00,
author = {D. Torres Roman and
A. Larios and
M. Guzman},
title = {A Chip for a Routing Table Based on a Novel Modified Trie Algorithm},
journal = {{VLSI} Design},
volume = {11},
number = {4},
pages = {405--415},
year = {2000},
url = {https://doi.org/10.1155/2000/81057},
doi = {10.1155/2000/81057},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/RomanLG00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/Saab00,
author = {Youssef Saab},
title = {Guest Editorial},
journal = {{VLSI} Design},
volume = {11},
number = {3},
year = {2000},
url = {https://doi.org/10.1155/2000/96528},
doi = {10.1155/2000/96528},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/Saab00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/Saab00a,
author = {Youssef Saab},
title = {A New 2-way Multi-level Partitioning Algorithm},
journal = {{VLSI} Design},
volume = {11},
number = {3},
pages = {301--310},
year = {2000},
url = {https://doi.org/10.1155/2000/65821},
doi = {10.1155/2000/65821},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/Saab00a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/Simeu00,
author = {Emmanuel Simeu},
title = {Optimal Detector Design for On-line Testing of Linear Analog Systems},
journal = {{VLSI} Design},
volume = {11},
number = {1},
pages = {59--74},
year = {2000},
url = {https://doi.org/10.1155/2000/92954},
doi = {10.1155/2000/92954},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/Simeu00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/WangCC00,
author = {Chua{-}Chin Wang and
Yu{-}Tsun Chien and
Ying{-}Pei Chen},
title = {A Practical Load-optimized {VCO} Design for Low-jitter 5V 500 MHz
Digital Phase-locked Loop},
journal = {{VLSI} Design},
volume = {11},
number = {2},
pages = {107--113},
year = {2000},
url = {https://doi.org/10.1155/2000/52658},
doi = {10.1155/2000/52658},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/WangCC00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/WangHC00,
author = {Chua{-}Chin Wang and
Chenn{-}Jung Huang and
I{-}Yen Chang},
title = {Design and Analysis of Radix-8/4/2 64b/32b Integer Divider Using {COMPASS}
Cell Library},
journal = {{VLSI} Design},
volume = {11},
number = {4},
pages = {331--338},
year = {2000},
url = {https://doi.org/10.1155/2000/69148},
doi = {10.1155/2000/69148},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/WangHC00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/WangHL00,
author = {Chua{-}Chin Wang and
Chenn{-}Jung Huang and
Po{-}Ming Lee},
title = {Design and Analysis of Digital Ratioed Compressors for Inner Product
Processing},
journal = {{VLSI} Design},
volume = {11},
number = {4},
pages = {353--361},
year = {2000},
url = {https://doi.org/10.1155/2000/72812},
doi = {10.1155/2000/72812},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/WangHL00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/ZhangZ00,
author = {Yanjun Zhang and
Si{-}Qing Zheng},
title = {An Efficient Parallel {VLSI} Sorting Architecture},
journal = {{VLSI} Design},
volume = {11},
number = {2},
pages = {137--147},
year = {2000},
url = {https://doi.org/10.1155/2000/14617},
doi = {10.1155/2000/14617},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/ZhangZ00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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