• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 31 matches

• 2000
• 
  Shawki Areibi, Anthony Vannelli:
  Tabu Search: A Meta Heuristic for Netlist Partitioning. VLSI Design 11(3): 259-283 (2000)
• 
  Roman P. Bazylevych, R. A. Melnyk, O. G. Rybak:
  Circuit Partitioning for FPGAs by the Optimal Circuit Reduction Method. VLSI Design 11(3): 237-248 (2000)
• 
  Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov:
  Iterative Partitioning with Varying Node Weights. VLSI Design 11(3): 249-258 (2000)
• 
  Sao-Jie Chen, Chung-Kuan Cheng:
  Tutorial on VLSI Partitioning. VLSI Design 11(3): 175-218 (2000)
• 
  Chien-In Henry Chen, Yingjie Zhou:
  Configurable 2-D Linear Feedback Shift Registers for VLSI Built-in Self-test Designs. VLSI Design 11(2): 149-159 (2000)
• 
  Andrew G. Dempster:
  Graphical Design Techniques for Fixed-point Multiplication. VLSI Design 11(4): 363-379 (2000)
• 
  Alexej Dmitriev, Valerij V. Saposhnikov, Vladimir V. Saposhnikov, Michael Gössel, V. Moshanin, Andrej A. Morosov:
  New Self-dual Circuits for Error Detection and Testing. VLSI Design 11(1): 1-21 (2000)
• 
  Bogdan J. Falkowski, Chip-Hong Chang:
  Minimization of k-Variable-Mixed-Polarity Reed-Muller Expansions. VLSI Design 11(4): 311-320 (2000)
• 
  Bogdan J. Falkowski, Radomir S. Stankovic:
  Spectral Interpretation and Applications of Decision Diagrams. VLSI Design 11(2): 85-105 (2000)
• 
  Ilhan Hatirnaz, Frank K. Gürkaynak, Yusuf Leblebici:
  A Modular and Scalable Architecture for the Realization of High-speed Programmable Rank Order Filters Using Threshold Logic. VLSI Design 11(2): 115-128 (2000)
• 
  George Karypis, Vipin Kumar:
  Multilevel k-way Hypergraph Partitioning. VLSI Design 11(3): 285-300 (2000)
• 
  Xrysovalantis Kavousianos, Dimitris Nikolos, G. Sidiropoulos:
  Novel Single and Double Output TSC CMOS Checkers for m-out-of-n Codes. VLSI Design 11(1): 35-45 (2000)
• 
  Dong-Wook Kim, Tae-Yong Choi:
  Delay Time Estimation Model for Large Digital CMOS Circuits. VLSI Design 11(2): 161-173 (2000)
• 
  Parag K. Lala:
  Guest Editorial. VLSI Design 11(1) (2000)
• 
  Huiqun Liu, Kai Zhu, D. F. Wong:
  FPGA Partitioning with Complex Resource Constraints. VLSI Design 11(3): 219-235 (2000)
• 
  Antonio J. López-Martín, Alfonso Carlosena:
  Design of MOS-translinear Multiplier/Dividers in Analog VLSI. VLSI Design 11(4): 321-329 (2000)
• 
  S. Masupe, Tughrul Arslan:
  Low Power VLSI Implementation of the DCT on Single Multiplier DSP Processors. VLSI Design 11(4): 397-403 (2000)
• 
  Anzhela Yu. Matrosova, Ilya Levin, Sergey Ostanin:
  Self-checking Synchronous FSM Network Design with Low Overhead. VLSI Design 11(1): 47-58 (2000)
• 
  Cecilia Metra, Michele Favalli, Bruno Riccò:
  Signal Coding and CMOS Gates for Combinational Functional Blocks of Very Deep Submicron Self-checking Circuits. VLSI Design 11(1): 23-34 (2000)
• 
  Chaeryung Park, Taewhan Kim, C. L. Liu:
  An Integrated Approach to Data Path Synthesis for Behavioral-level Power Optimization. VLSI Design 11(4): 381-396 (2000)
• 
  L. M. Patnaik, Satrajit Gupta:
  Exact Output Response Computation of RC Interconnects Under General Polynomial Input Waveforms. VLSI Design 11(2): 75-84 (2000)
• 
  Esther Rodríguez-Villegas, Maria J. Avedillo, José M. Quintana, Gloria Huertas, Adoración Rueda:
  νMOS-based Sorter for Arithmetic Applications. VLSI Design 11(2): 129-136 (2000)
• 
  D. Torres Roman, J. Gonzalez, M. Guzman:
  A New Bus Assignment Algorithm for a Shared Bus Switch Fabric. VLSI Design 11(4): 339-351 (2000)
• 
  D. Torres Roman, A. Larios, M. Guzman:
  A Chip for a Routing Table Based on a Novel Modified Trie Algorithm. VLSI Design 11(4): 405-415 (2000)
• 
  Youssef Saab:
  Guest Editorial. VLSI Design 11(3) (2000)
• 
  Youssef Saab:
  A New 2-way Multi-level Partitioning Algorithm. VLSI Design 11(3): 301-310 (2000)
• 
  Emmanuel Simeu:
  Optimal Detector Design for On-line Testing of Linear Analog Systems. VLSI Design 11(1): 59-74 (2000)
• 
  Chua-Chin Wang, Yu-Tsun Chien, Ying-Pei Chen:
  A Practical Load-optimized VCO Design for Low-jitter 5V 500 MHz Digital Phase-locked Loop. VLSI Design 11(2): 107-113 (2000)
• 
  Chua-Chin Wang, Chenn-Jung Huang, I-Yen Chang:
  Design and Analysis of Radix-8/4/2 64b/32b Integer Divider Using COMPASS Cell Library. VLSI Design 11(4): 331-338 (2000)
• 
  Chua-Chin Wang, Chenn-Jung Huang, Po-Ming Lee:
  Design and Analysis of Digital Ratioed Compressors for Inner Product Processing. VLSI Design 11(4): 353-361 (2000)

skipping 1 more match