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@article{DBLP:journals/tc/LuoCLC19,
  author       = {Jing{-}Yuan Luo and
                  Hsiang{-}Yun Cheng and
                  Ing{-}Chao Lin and
                  Da{-}Wei Chang},
  title        = {{TAP:} Reducing the Energy of Asymmetric Hybrid Last-Level Cache via
                  Thrashing Aware Placement and Migration},
  journal      = {{IEEE} Trans. Computers},
  volume       = {68},
  number       = {12},
  pages        = {1704--1719},
  year         = {2019},
  url          = {https://doi.org/10.1109/TC.2019.2917208},
  doi          = {10.1109/TC.2019.2917208},
  timestamp    = {Tue, 26 Nov 2019 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tc/LuoCLC19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/islped/LiangCCCCS19,
  author       = {Yu{-}Pei Liang and
                  Tseng{-}Yi Chen and
                  Yuan{-}Hao Chang and
                  Shuo{-}Han Chen and
                  Pei{-}Yu Chen and
                  Wei{-}Kuan Shih},
  title        = {Rethinking Last-level-cache Write-back Strategy for {MLC} {STT-RAM}
                  Main Memory with Asymmetric Write Energy},
  booktitle    = {2019 {IEEE/ACM} International Symposium on Low Power Electronics and
                  Design, {ISLPED} 2019, Lausanne, Switzerland, July 29-31, 2019},
  pages        = {1--6},
  publisher    = {{IEEE}},
  year         = {2019},
  url          = {https://doi.org/10.1109/ISLPED.2019.8824899},
  doi          = {10.1109/ISLPED.2019.8824899},
  timestamp    = {Mon, 03 Jan 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/islped/LiangCCCCS19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/ChengZSIJL016,
  author       = {Hsiang{-}Yun Cheng and
                  Jishen Zhao and
                  Jack Sampson and
                  Mary Jane Irwin and
                  Aamer Jaleel and
                  Yu Lu and
                  Yuan Xie},
  title        = {{LAP:} Loop-Block Aware Inclusion Properties for Energy-Efficient
                  Asymmetric Last Level Caches},
  booktitle    = {43rd {ACM/IEEE} Annual International Symposium on Computer Architecture,
                  {ISCA} 2016, Seoul, South Korea, June 18-22, 2016},
  pages        = {103--114},
  publisher    = {{IEEE} Computer Society},
  year         = {2016},
  url          = {https://doi.org/10.1109/ISCA.2016.19},
  doi          = {10.1109/ISCA.2016.19},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/ChengZSIJL016.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/samos/GutierrezDM14,
  author       = {Anthony Gutierrez and
                  Ronald G. Dreslinski and
                  Trevor N. Mudge},
  title        = {Evaluating private vs. shared last-level caches for energy efficiency
                  in asymmetric multi-cores},
  booktitle    = {XIVth International Conference on Embedded Computer Systems: Architectures,
                  Modeling, and Simulation, {SAMOS} 2014, Agios Konstantinos, Samos,
                  Greece, July 14-17, 2014},
  pages        = {191--198},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/SAMOS.2014.6893211},
  doi          = {10.1109/SAMOS.2014.6893211},
  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/samos/GutierrezDM14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}