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found 25 matches

• 1996
• 
  D. K. Arvind, Vinod E. F. Rebello:
  Static scheduling of instructions on micronet-based asynchronous processors. ASYNC 1996: 80-91
• 
  Peter A. Beerel, Kenneth Y. Yun, Wei-Chun Chou:
  Optimizing average-case delay in technology mapping of burst-mode circuits. ASYNC 1996: 244-260
• 
  Kees van Berkel, Arjan Bink:
  Single-track handshake signaling with application to micropipelines and handshake circuits. ASYNC 1996: 122-133
• 
  Steven M. Burns:
  General conditions for the decomposition of state holding elements. ASYNC 1996: 48-57
• 
  Martin E. Bush, Mark B. Josephs:
  Some limitations to speed-independence in asynchronous circuits. ASYNC 1996: 104-111
• 
  Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alex Yakovlev:
  Complete state encoding based on the theory of regions. ASYNC 1996: 36-47
• 
  Clark Foley:
  Characterizing metastability. ASYNC 1996: 175-184
• 
  Stephen B. Furber, Jianwei Liu:
  Dynamic logic in four-phase micropipelines. ASYNC 1996: 11-16
• 
  Jim D. Garside, Steve Temple, Rahul Mehra:
  The AMULET2e cache system. ASYNC 1996: 208-217
• 
  Eckhard Grass, Richard C. S. Morling, Izzet Kale:
  Activity-Monitoring Completion-Detection (AMCD): a new single rail approach to achieve self-timing. ASYNC 1996: 143-149
• 
  Rakefet Kol, Ran Ginosar, Goel Samuel:
  Statechart methodology for the design, validation, and synthesis of large scale asynchronous systems. ASYNC 1996: 164-174
• 
  Tilman Kolks, Steven Vercauteren, Bill Lin:
  Control resynthesis for control-dominated asynchronous designs. ASYNC 1996: 233-243
• 
  Paul G. Lucassen, Jan Tijmen Udding:
  On the correctness of the Sproull counterflow pipeline processor. ASYNC 1996: 112-120
• 
  Masaaki Maezawa, Itaru Kurosawa, Yoshio Kameda, Takashi Nanya:
  Pulse-driven dual-rail logic gate family based on rapid single-flux-quantum (RSFQ) devices for asynchronous circuits. ASYNC 1996: 134-142
• 
  Toshiyuki Miyamoto, Sadatoshi Kumagai:
  An efficient algorithm for deriving logic functions of asynchronous circuits. ASYNC 1996: 30-35
• 
  Lars Skovby Nielsen, Jens Sparsø:
  A low-power asynchronous data-path for a FIR filter bank. ASYNC 1996: 197-207
• 
  Marco A. Peña, Jordi Cortadella:
  Combining process algebras and Petri nets for the specification and synthesis of asynchronous circuits. ASYNC 1996: 222-232
• 
  William F. Richardson, Erik Brunvand:
  Fred: an architecture for a self-timed decoupled computer. ASYNC 1996: 60-68
• 
  Per Torstein Røine:
  A system for asynchronous high-speed chip to chip communication. ASYNC 1996: 2-10
• 
  Nozar Tabrizi, Michael J. Liebelt, Kamran Eshraghian:
  Dynamic hazards and speed independent delay model. ASYNC 1996: 94-103
• 
  José A. Tierno, Rajit Manohar, Alain J. Martin:
  The energy and entropy of VLSI computations. ASYNC 1996: 188-196
• 
  Tony Werner, Venkatesh Akella:
  Counterflow pipeline based dynamic instruction scheduling. ASYNC 1996: 69-79
• 
  Tomohiro Yoneda, Takashi Yoshikawa:
  Using partial orders for trace theoretic verification of asynchronous circuits. ASYNC 1996: 152-163
• 
  Kenneth Y. Yun, Peter A. Beerel, Julio Arceo:
  High-performance asynchronous pipeline circuits. ASYNC 1996: 17-28
• 
  2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96), March 18-21, 1996, Aizu-Wakamatsu, Fukushima, Japan. IEEE Computer Society 1996, ISBN 0-8186-7298-6 [contents]