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Publication search results
found 17 matches
- 2009
- Aneesh Aggarwal:
Complexity Effective Bypass Networks. Trans. High Perform. Embed. Archit. Compil. 2: 201-221 (2009) - Minwook Ahn, Yunheung Paek:
Fast Code Generation for Embedded Processors with Aliased Heterogeneous Registers. Trans. High Perform. Embed. Archit. Compil. 2: 149-172 (2009) - Major Bhadauria, Sally A. McKee, Karan Singh, Gary S. Tyson:
Data Cache Techniques to Save Power and Deliver High Performance in Embedded Systems. Trans. High Perform. Embed. Archit. Compil. 2: 65-84 (2009) - Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa:
Compiler Support for Code Size Reduction Using a Queue-Based Processor. Trans. High Perform. Embed. Archit. Compil. 2: 269-285 (2009) - Dominique Chanet, Javier Cabezas, Enric Morancho, Nacho Navarro, Koen De Bosschere:
Linux Kernel Compaction through Cold Code Swapping. Trans. High Perform. Embed. Archit. Compil. 2: 173-200 (2009) - Woojin Choi, Seok-Jun Park, Michel Dubois:
Accurate Instruction Pre-scheduling in Dynamically Scheduled Processors. Trans. High Perform. Embed. Archit. Compil. 2: 107-127 (2009) - Amit Golander, Shlomo Weiss:
Reexecution and Selective Reuse in Checkpoint Processors. Trans. High Perform. Embed. Archit. Compil. 2: 242-268 (2009) - Chunling Hu, Daniel A. Jiménez, Ulrich Kremer:
Combining Edge Vector and Event Counter for Time-Dependent Power Behavior Characterization. Trans. High Perform. Embed. Archit. Compil. 2: 85-104 (2009) - Khaled Z. Ibrahim, Smaïl Niar:
Power-Aware Bus Coscheduling for Periodic Realtime Applications Running on Multiprocessor SoC. Trans. High Perform. Embed. Archit. Compil. 2: 286-306 (2009) - Georgios Keramidas, Polychronis Xekalakis, Stefanos Kaxiras:
Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches. Trans. High Perform. Embed. Archit. Compil. 2: 4-22 (2009) - Simon Kluyskens, Lieven Eeckhout:
Branch Predictor Warmup for Sampled Simulation through Branch History Matching. Trans. High Perform. Embed. Archit. Compil. 2: 45-64 (2009) - Patrick Mahoney, Yvon Savaria, Guy Bois, Patrice Plante:
Performance Characterization for the Implementation of Content Addressable Memories Based on Parallel Hashing Memories. Trans. High Perform. Embed. Archit. Compil. 2: 307-325 (2009) - Vijay Nagarajan, Rajiv Gupta, Arvind Krishnaswamy:
Compiler-Assisted Memory Encryption for Embedded Processors. Trans. High Perform. Embed. Archit. Compil. 2: 23-44 (2009) - Christine Rochange, Pascal Sainrat:
A Context-Parameterized Model for Static Analysis of Execution Times. Trans. High Perform. Embed. Archit. Compil. 2: 222-241 (2009) - Per Stenström, David B. Whalley:
Introduction. Trans. High Perform. Embed. Archit. Compil. 2: 3 (2009) - Hans Vandierendonck, André Seznec:
Fetch Gating Control through Speculative Instruction Window Weighting. Trans. High Perform. Embed. Archit. Compil. 2: 128-148 (2009) - Per Stenström:
Transactions on High-Performance Embedded Architectures and Compilers II. Lecture Notes in Computer Science 5470, Springer 2009, ISBN 978-3-642-00903-7 [contents]
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