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Publication search results
found 26 matches
- 1991
- Poras T. Balsara, Mary Jane Irwin:
Image processing on a memory array architecture. J. VLSI Signal Process. 2(4): 313-324 (1991) - Ron Bourassa, Tim Coffman, Joe Brewer:
Ultra large scale static rams. J. VLSI Signal Process. 2(4): 301-311 (1991) - Wayne P. Burleson, Louis L. Scharf:
A VLSI design methodology for distributed arithmetic. J. VLSI Signal Process. 2(4): 235-252 (1991) - Virginio Cantoni, V. Gesu, Marco Ferretti, Stefano Levialdi, Roberto M. Negrini, Renato Stefanelli:
The PAPIA system. J. VLSI Signal Process. 2(4): 195-217 (1991) - Marios D. Dikaiakos, Kenneth Steiglitz:
Comparison of tree and straight-line clocking for long systolic arrays. J. VLSI Signal Process. 2(4): 287-299 (1991) - Vijay K. Jain, David L. Landis, David C. Keezer, K. T. Wilson, Denny Whittaker:
Wafer Scale Integration: A university perspective. J. VLSI Signal Process. 2(4): 253-269 (1991) - R. M. Lea:
WASP: A WSI Associative String Processor. J. VLSI Signal Process. 2(4): 271-285 (1991) - Richard C. North, Walter H. Ku:
beta-bit serial/parallel multipliers. J. VLSI Signal Process. 2(4): 219-233 (1991) - 1990
- James B. Clary:
Signal processing architecture assessment. J. VLSI Signal Process. 2(2): 117-121 (1990) - Luigi Dadda:
A polyphase architecture for serial-input convolvers. J. VLSI Signal Process. 2(1): 17-27 (1990) - Daniel J. Dechant:
The Advanced Onboard Signal Processor (AOSP). J. VLSI Signal Process. 2(2): 69-78 (1990) - F. M. F. Gaston, George W. Irwin, John G. McWhirter:
Systolic square root covariance Kalman filtering. J. VLSI Signal Process. 2(1): 37-49 (1990) - John A. Graniero, Claud N. Bain:
Introduction. J. VLSI Signal Process. 2(2): 67 (1990) - Mark R. Greenstreet, Kenneth Steiglitz:
Bubbles can make self-timed pipelines fast. J. VLSI Signal Process. 2(3): 139-148 (1990) - M. J. Iacoponi:
The Advanced Architecture On-board Processor signal processing testbed. J. VLSI Signal Process. 2(2): 89-101 (1990) - Graham A. Jullien, Subir Bandyopadhyay, William C. Miller, Majid Taheri:
A low-overhead scheme for testing a bit-level finite ring systolic array. J. VLSI Signal Process. 2(3): 131-137 (1990) - Tom Kean, John Gray:
Configurable hardware: Two case studies of micro-grain computation. J. VLSI Signal Process. 2(1): 9-16 (1990) - Sy-Yen Kuo, Kuochen Wang:
Fault diagnosis in reconfigurable VLSI and WSI processor arrays. J. VLSI Signal Process. 2(3): 173-187 (1990) - Stuart Lawson, Steve Summerfield:
The design of wave digital filters using fully pipelined bit-level systolic arrays. J. VLSI Signal Process. 2(1): 7 (1990) - Paul S. Lewis:
Systolic architectures for adaptive multichannel least squares lattice filters. J. VLSI Signal Process. 2(1): 29-36 (1990) - M. J. Little, R. David Etchells, Jan Grinberg, S. P. Laub, J. G. Nash, M. W. Yung:
The 3-D Computer. J. VLSI Signal Process. 2(2): 79-87 (1990) - Greg Melcher, Greg Thomas, David Kaplan:
The Navy's new standard digital signal processor, the AN/UYS-2. J. VLSI Signal Process. 2(2): 103-109 (1990) - Earl E. Swartzlander Jr.:
Editorial. J. VLSI Signal Process. 2(1): 5 (1990) - Earl E. Swartzlander Jr.:
Generic signal processor implementation with VHSIC. J. VLSI Signal Process. 2(2): 111-116 (1990) - Thomas L. Wernimont, David K. Hwang, W. Kent Fuchs:
CSP-based object-oriented description and simulation of a reconfigurable adaptive beamforming architecture using the OODRA workbench. J. VLSI Signal Process. 2(3): 159-172 (1990) - M. Yan, John V. McCanny:
A bit-level systolic architecture for implementing a VQ tree search. J. VLSI Signal Process. 2(3): 149-158 (1990)
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retrieved on 2024-10-07 16:38 CEST from data curated by the dblp team
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