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Hiroyuki Tomiyama
- > Home > Persons > Hiroyuki Tomiyama
Publications
- 2019
- [c74]Kenta Shirane, Takahiro Yamamoto, Ittetsu Taniguchi, Yuko Hara-Azumi, Shigeru Yamashita, Hiroyuki Tomiyama:
Maximum Error-Aware Design of Approximate Array Multipliers. ISOCC 2019: 73-74 - 2017
- [j46]Takahiro Yamamoto, Ittetsu Taniguchi, Hiroyuki Tomiyama, Shigeru Yamashita, Yuko Hara-Azumi:
A Systematic Methodology for Design and Worst-Case Error Analysis of Approximate Array Multipliers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(7): 1496-1499 (2017) - 2016
- [c62]Takahiro Yamamoto, Ittetsu Taniguchi, Hiroyuki Tomiyama, Shigeru Yamashita, Yuko Hara-Azumi:
A systematic methodology for design and analysis of approximate array multipliers. APCCAS 2016: 352-354 - 2015
- [c61]Stefan Hadjis, Andrew Canis, Ryoya Sobue, Yuko Hara-Azumi, Hiroyuki Tomiyama, Jason Helge Anderson:
Profiling-driven multi-cycling in FPGA high-level synthesis. DATE 2015: 31-36 - 2014
- [j37]Ittetsu Taniguchi, Junya Kaida, Takuji Hieda, Yuko Hara-Azumi, Hiroyuki Tomiyama:
Static Mapping with Dynamic Switching of Multiple Data-Parallel Applications on Embedded Many-Core SoCs. IEICE Trans. Inf. Syst. 97-D(11): 2827-2834 (2014) - [j33]Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada:
Impact of Resource Sharing and Register Retiming on Area and Performance of FPGA-based Designs. IPSJ Trans. Syst. LSI Des. Methodol. 7: 37-45 (2014) - 2013
- [j32]Junya Kaida, Yuko Hara-Azumi, Takuji Hieda, Ittetsu Taniguchi, Hiroyuki Tomiyama, Koji Inoue:
Static Mapping of Multiple Data-Parallel Applications on Embedded Many-Core SoCs. IEICE Trans. Inf. Syst. 96-D(10): 2268-2271 (2013) - [j28]Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada:
Quantitative Evaluation of Resource Sharing in High-level Synthesis Using Realistic Benchmarks. IPSJ Trans. Syst. LSI Des. Methodol. 6: 122-126 (2013) - [c52]Yuko Hara-Azumi, Hiroyuki Tomiyama:
Cost-efficient scheduling in high-level synthesis for Soft-Error Vulnerability Mitigation. ISQED 2013: 502-507 - 2012
- [c50]Yuko Hara, Hiroyuki Tomiyama:
Clock-constrained simultaneous allocation and binding for multiplexer optimization in high-level synthesis. ASP-DAC 2012: 251-256 - [c49]Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada:
Selective Resource Sharing with RT-Level Retiming for Clock Enhancement in High-Level Synthesis. HPCC-ICESS 2012: 1534-1540 - [c46]Junya Kaida, Takuji Hieda, Ittetsu Taniguchi, Hiroyuki Tomiyama, Yuko Hara-Azumi, Koji Inoue:
Task mapping techniques for embedded many-core SoCs. ISOCC 2012: 204-207 - 2010
- [j22]Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada:
Partitioning of Behavioral Descriptions with Exploiting Function-Level Parallelism. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(2): 488-499 (2010) - [c37]Toshinobu Matsuba, Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada:
Aggressive Register Unsharing Based on SSA Transformation for Clock Enhancement in High-Level Synthesis. DELTA 2010: 87-92 - 2009
- [j15]Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada:
Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis. J. Inf. Process. 17: 242-254 (2009) - 2008
- [j10]Seiya Shibata, Shinya Honda, Yuko Hara, Hiroyuki Tomiyama, Hiroaki Takada:
Embedded System Covalidation with RTOS Model and FPGA. IPSJ Trans. Syst. LSI Des. Methodol. 1: 126-130 (2008) - [c28]Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii:
CHStone: A benchmark program suite for practical C-based high-level synthesis. ISCAS 2008: 1192-1195 - 2007
- [j9]Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada:
Function Call Optimization for Efficient Behavioral Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(9): 2032-2036 (2007) - [j8]Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii:
Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12): 2853-2862 (2007) - [c25]Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii:
Complexity-constrainted partitioning of sequential programs for efficient behavioral synthesis. ACM Great Lakes Symposium on VLSI 2007: 365-370 - [c24]Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii:
Behavioral Synthesis of Double-Precision Floating-Point Adders with Function-Level Transformations: A Case Study. ICESS 2007: 261-270 - 2006
- [c20]Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada:
Function Call Optimization in Behavioral Synthesis. DSD 2006: 522-529
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