default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDDATE 2015: Grenoble, France
- Wolfgang Nebel, David Atienza:
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, Grenoble, France, March 9-13, 2015. ACM 2015, ISBN 978-3-9815370-4-8
Adaptability for low power computing
- Jianfeng Liu, Mi-Suk Hong, Kyung Tae Do, Jung Yun Choi, Jaehong Park, Mohit Kumar, Manish Kumar, Nikhil Tripathi, Abhishek Ranjan:
Clock domain crossing aware sequential clock gating. 1-6 - Hehe Li, Yongpan Liu, Qinghang Zhao, Yizi Gu, Xiao Sheng, Guangyu Sun, Chao Zhang, Meng-Fan Chang, Rong Luo, Huazhong Yang:
An energy efficient backup scheme with low inrush current for nonvolatile SRAM in energy harvesting sensor nodes. 7-12 - Chenchen Fu, Minming Li, Chun Jason Xue:
Race to idle or not: balancing the memory sleep time with DVS for energy minimization. 13-18 - Xue Lin, Yanzhi Wang, Massoud Pedram, Jaemin Kim, Naehyuck Chang:
Event-driven and sensorless photovoltaic system reconfiguration for electric vehicles. 19-24
System level design methods
- Farzad Samie, Lars Bauer, Chih-Ming Hsieh, Jörg Henkel:
Online binding of applications to multiple clock domains in shared FPGA-based systems. 25-30 - Stefan Hadjis, Andrew Canis, Ryoya Sobue, Yuko Hara-Azumi, Hiroyuki Tomiyama, Jason Helge Anderson:
Profiling-driven multi-cycling in FPGA high-level synthesis. 31-36 - Jung-Eun Kim, Tarek F. Abdelzaher, Lui Sha:
Schedulability bound for integrated modular avionics partitions. 37-42
Automotive systems and smart energy systems
- Anup Das, Akash Kumar, Bharadwaj Veeravalli, Rishad Ahmed Shafik, Geoff V. Merrett, Bashir M. Al-Hashimi:
Workload uncertainty characterization and adaptive frequency scaling for energy minimization of embedded systems. 43-48 - Jan R. Seyler, Thilo Streichert, Michael Glaß, Nicolas Navet, Jürgen Teich:
Formal analysis of the startup delay of SOME/IP service discovery. 49-54 - Sivakumar Thangamuthu, Nicola Concer, Pieter J. L. Cuijpers, Johan J. Lukkien:
Analysis of ethernet-switch traffic shapers for in-vehicle networking applications. 55-60 - Christian Herber, Andre Oliver Richter, Thomas Wild, Andreas Herkersdorf:
Real-time capable CAN to AVB ethernet gateway using frame aggregation and scheduling. 61-66
Power of assertions
- Alessandro Danese, Tara Ghasempouri, Graziano Pravadelli:
Automatic extraction of assertions from execution traces of behavioural models. 67-72 - Pouya Taatizadeh, Nicola Nicolici:
A methodology for automated design of embedded bit-flips detectors in post-silicon validation. 73-78 - Monica Farkash, Bryan G. Hickerson, Balavinayagam Samynathan:
Data mining diagnostics and bug MRIs for HW bug localization. 79-84 - Nicola Bombieri, Riccardo Filippozzi, Graziano Pravadelli, Francesco Stefanni:
RTL property abstraction for TLM assertion-based verification. 85-90
Design and analysis of dependable systems
- Carles Hernández, Jaume Abella:
Low-cost checkpointing in automotive safety-relevant systems. 91-96 - Faramarz Khosravi, Malte Müller, Michael Glaß, Jürgen Teich:
Uncertainty-aware reliability analysis and optimization. 97-102 - Shahrzad Mirkhani, Subhasish Mitra, Chen-Yong Cher, Jacob A. Abraham:
Efficient soft error vulnerability estimation of complex designs. 103-108 - Xuanle Ren, Vítor Grade Tavares, R. D. (Shawn) Blanton:
Detection of illegitimate access to JTAG via statistical learning in chip. 109-114
Compilation and code transformations for reconfigurable computing
- Shouyi Yin, Dajiang Liu, Leibo Liu, Shaojun Wei, Yike Guo:
Joint affine transformation and loop pipelining for mapping nested loop on CGRAs. 115-120 - ShriHari RajendranRadhika, Aviral Shrivastava, Mahdi Hamzeh:
Path selection based acceleration of conditionals in CGRAs. 121-126 - Meha Kainth, Lekshmi Krishnan, Chaitra Narayana, Sandesh Gubbi Virupaksha, Russell Tessier:
Hardware-assisted code obfuscation for FPGA soft microprocessors. 127-132
Passive implementation attacks and countermeasures
- Valentina Banciu, Elisabeth Oswald, Carolyn Whitnall:
Reliable information extraction for single trace attacks. 133-138 - Daehyun Strobel, Florian Bache, David F. Oswald, Falk Schellenberg, Christof Paar:
Scandalee: a side-channel-based disassembler using local electromagnetic emanations. 139-144 - Santos Merino Del Pozo
, François-Xavier Standaert, Dina Kamel, Amir Moradi:
Side-channel attacks from static power: when should we care? 145-150 - Jinyong Lee, Yongje Lee, Hyungon Moon, Ingoo Heo, Yunheung Paek:
Extrax: security extension to extract cache resident information for snoop-based external monitors. 151-156
Loop acceleration
- Pham Nam Khanh, Amit Kumar Singh, Akash Kumar, Khin Mi Mi Aung:
Exploiting loop-array dependencies to accelerate the design space exploration with high level synthesis. 157-162 - Alessandro Cilardo, Luca Gallo:
Interplay of loop unrolling and multidimensional memory partitioning in HLS. 163-168 - Maurice Peemen, Bart Mesman, Henk Corporaal:
Inter-tile reuse optimization applied to bandwidth constrained embedded accelerators. 169-174
Tackling memory walls with emerging architectures and technologies
- Yuan Yao, Guanhua Wang, Zhiguo Ge, Tulika Mitra, Wenzhi Chen, Naxin Zhang:
SelectDirectory: a selective directory for cache coherence in many-core architectures. 175-180 - Ashish Ranjan, Shankar Ganesh Ramasubramanian, Rangharajan Venkatesan, Vijay S. Pai, Kaushik Roy, Anand Raghunathan:
DyReCTape: a <u>dy</u>namically <u>re</u>configurable <u>c</u>ache using domain wall memory <u>tape</u>s. 181-186 - Shouyi Yin, Jiakun Li, Leibo Liu, Shaojun Wei, Yike Guo:
Cooperatively managing dynamic writeback and insertion policies in a last-level DRAM cache. 187-192 - Manil Dev Gomony, Jamie Garside, Benny Akesson, Neil C. Audsley, Kees Goossens:
A generic, scalable and globally arbitrated memory tree for shared DRAM access in real-time systems. 193-198
Breaking simulation boundaries
- Mingsong Chen, Daian Yue, Xiaoke Qin, Xin Fu, Prabhat Mishra:
Variation-aware evaluation of MPSoC task allocation and scheduling strategies using statistical model checking. 199-204 - Xiaoming Chen, Yu Wang, Huazhong Yang:
A fast parallel sparse solver for SPICE-based circuit simulators. 205-210 - Xinke Chen, Guangfei Zhang, Huandong Wang, Ruiyang Wu, Peng Wu, Longbing Zhang:
MRP: mix real cores and pseudo cores for FPGA-based chip-multiprocessor simulation. 211-216 - Christoph Gerum, Oliver Bringmann, Wolfgang Rosenstiel:
Source level performance simulation of GPU cores. 217-222
Model-based analysis and verification
- Nan Guan, Yue Tang, Yang Wang, Wang Yi:
Delay analysis of structural real-time workload. 223-228 - Daniel Kroening, Lihao Liang, Tom Melham, Peter Schrammel, Michael Tautschnig:
Effective verification of low-level software with nested interrupts. 229-234 - BaekGyu Kim, Lu Feng, Linh T. X. Phan, Oleg Sokolsky, Insup Lee:
Platform-specific timing verification framework in model-based implementation. 235-240 - Andreas Ibing:
Architecture description language based retargetable symbolic execution. 241-246
Hot topic - design methodologies for a cyber-physical systems approach to personalized medicine-on-a-chip: challenges and opportunities
- Mohamed Ibrahim, Krishnendu Chakrabarty:
Error recovery in digital microfluidics for personalized medicine. 247-252 - Paul Bogdan:
A cyber-physical systems approach to personalized medicine: challenges and opportunities for noc-based multicore platforms. 253-258 - Turbo Majumder, Partha Pratim Pande, Ananth Kalyanaraman:
On-chip network-enabled many-core architectures for computational biology applications. 259-264
Interactive presentations
- Fabian Oboril, Jos Ewert, Mehdi Baradaran Tahoori:
High-resolution online power monitoring for modern microprocessors. 265-268 - Andres Gomez, Christian Pinto, Andrea Bartolini, Davide Rossi, Luca Benini, Hamed Fatemi, José Pineda de Gyvez:
Reducing energy consumption in microcontroller-based platforms with low design margin co-processors. 269-272 - Mahdi Jelodari Mamaghani, Jim D. Garside, Doug A. Edwards:
De-elastisation: from asynchronous dataflows to synchronous circuits. 273-276 - Jannis Stoppe, Robert Wille, Rolf Drechsler:
Automated feature localization for dynamically generated SystemC designs. 277-280 - Matthias Kauer, Swaminathan Narayanaswamy, Martin Lukasiewycz, Sebastian Steinhorst, Samarjit Chakraborty:
Inductor optimization for active cell balancing using geometric programming. 281-284 - Philipp Mundhenk, Sebastian Steinhorst, Martin Lukasiewycz, Suhaib A. Fahmy, Samarjit Chakraborty:
Lightweight authentication for secure automotive networks. 285-288 - Michael Shoniker, Bruce F. Cockburn, Jie Han, Witold Pedrycz:
Minimizing the number of process corner simulations during design verification. 289-292 - Ke Chen, Fabrizio Lombardi, Jie Han:
An approximate voting scheme for reliable computing. 293-296 - Rochus Nowosielski, Lukas Gerlach, Stephan Bieband, Guillermo Payá-Vayá, Holger Blume:
FLINT: layout-oriented FPGA-based methodology for fault tolerant ASIC design. 297-300 - Sam Skalicky, Andrew G. Schmidt, Sonia López, Matthew French:
A unified hardware/software MPSoC system construction and run-time framework. 301-304 - Shakith Fernando, Mark Wijtvliet, Cedric Nugteren, Akash Kumar, Henk Corporaal:
(AS)2: accelerator synthesis using algorithmic skeletons for rapid design space exploration. 305-308 - Philipp Niemann, Frank Hilken, Martin Gogolla, Robert Wille:
Assisted generation of frame conditions for formal models. 309-312 - Julien Deantoni, Papa Issa Diallo, Ciprian Teodorov, Joël Champeau, Benoît Combemale:
Towards a meta-language for the concurrency concern in DSLs. 313-316 - Antoine Faravelon, Nicolas Fournel, Frédéric Pétrot:
Fast and accurate branch predictor simulation. 317-320 - Wisam Kadry, Dmitry Krestyashyn, Arkadiy Morgenshtein, Amir Nahir, Vitali Sokhin, Jin Sung Park, Sung-Boem Park, Wookyeong Jeong, Jae-Cheol Son:
Comparative study of test generation methods for simulation accelerators. 321-324 - Wan-Chen Weng, Yung-Chih Chen, Jui-Hung Chen, Ching-Yi Huang, Chun-Yao Wang:
Using structural relations for checking combinationality of cyclic circuits. 325-328 - Andrws Vieira, Pedro Faustini, Luigi Carro, Érika F. Cota:
NFRs early estimation through software metrics. 329-332
Implementation and verification of security components
- Charalambos Konstantinou, Anastasis Keliris, Michail Maniatakos:
Privacy-preserving functional IP verification utilizing fully homomorphic encryption. 333-338 - Ruan de Clercq, Sujoy Sinha Roy, Frederik Vercauteren, Ingrid Verbauwhede:
Efficient software implementation of ring-LWE encryption. 339-344 - Bohan Yang, Vladimir Rozic, Nele Mentens, Wim Dehaene, Ingrid Verbauwhede:
Embedded HW/SW platform for on-the-fly testing of true random number generators. 345-350
Multi-/manycore scheduling
- Chien-Hui Liao, Charles H.-P. Wen, Krishnendu Chakrabarty:
An online thermal-constrained task scheduler for 3D multi-core processors. 351-356 - Alexander Biewer, Benjamin Andres, Jens Gladigau, Torsten Schaub, Christian Haubelt:
A symbolic system synthesis approach for hard real-time systems based on coordinated SMT-solving. 357-362 - Xi Zhang, Haris Javaid, Muhammad Shafique, Jorgen Peddersen, Jörg Henkel, Sri Parameswaran:
E-pipeline: elastic hardware/software pipelines on a many-core fabric. 363-368
Exploring reliability and efficiency tradeoffs at the architectural level
- Jingweijia Tan, Zhi Li, Xin Fu:
Soft-error reliability and power co-optimization for GPGPUS register file using resistive memory. 369-374 - Kaige Yan, Xin Fu:
Energy-efficient cache design in emerging mobile platforms: the implications and optimizations. 375-380 - Jeremy Constantin, Lai Wang, Georgios Karakonstantis, Anupam Chattopadhyay, Andreas Burg:
Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment. 381-386 - Muhammad Shafique, Dennis Gnad, Siddharth Garg, Jörg Henkel:
Variability-aware dark silicon management in on-chip many-core systems. 387-392
Industrial test and validation experiments
- Alejandra Ruiz, Alberto Melzi, Tim Kelly:
Systematic application of ISO 26262 on a SEooC: Support by applying a systematic reuse approach. 393-396 - Franck Wartel, Leonidas Kosmidis, Adriana Gogonel, Andrea Baldovin, Zoë R. Stephenson, Benoit Triquet, Eduardo Quiñones, Code Lo, Enrico Mezzetti, Ian Broster, Jaume Abella, Liliana Cucu-Grosjean, Tullio Vardanega, Francisco J. Cazorla:
Timing analysis of an avionics case study on complex hardware/software platforms. 397-402 - Torsten Reich, Benjamin Prautsch, Uwe Eichler, R. Buhl:
Silicon proof of the intelligent analog IP design flow for flexible automotive components. 403-404 - Fabien Teysseyre, David Navarro, Ian O'Connor, Francesco Cascio, Fabio Cenni, Olivier Guillaume:
Fast optical simulation from a reduced set of impulse responses using SystemC-AMS. 405-409 - Stephen Bergman, Gabor Bobok, Walter Kowalski, Shlomit Koyfman, Shiri Moran, Ziv Nevo, Avigail Orni, Viresh Paruthi, Wolfgang Roesner, Gil Shurek, Vasantha Vuyyuru:
Designer-level verification: an industrial experience story. 410-411 - Vibhu Sharma:
Minimum current consumption transition time optimization methodology for low power CTS. 412-416
Online testing and reliable memories
- Michail Mavropoulos, Georgios Keramidas, Dimitris Nikolos:
A defect-aware reconfigurable cache architecture for low-vccmin DVFS-enabled systems. 417-422 - Ying Zhang, Zebo Peng, Jianhui Jiang, Huawei Li, Masahiro Fujita:
Temperature-aware software-based self-testing for delay faults. 423-428 - T. Nandha Kumar, Haider A. F. Almurib, Fabrizio Lombardi:
Operational fault detection and monitoring of a memristor-based LUT. 429-434 - Mohammad Hashem Haghbayan, Amir-Mohammad Rahmani, Mohammad Fattah, Pasi Liljeberg, Juha Plosila, Zainalabedin Navabi, Hannu Tenhunen:
Power-aware online testing of manycore systems in the dark silicon era. 435-440
How resilient are emerging technologies?
- M. Saliva, Florian Cacho, Vincent Huard, X. Federspiel, D. Angot, Ahmed Benhassain, Alain Bravaix, Lorena Anghel:
Digital circuits reliability with in-situ monitors in 28nm fully depleted SOI. 441-446 - Elena I. Vatajelu, Rosa Rodríguez-Montañés, Marco Indaco, Michel Renovell, Paolo Prinetto, Joan Figueras:
Read/write robustness estimation metrics for spin transfer torque (STT) MRAM cell. 447-452 - Hassan Ghasemzadeh Mohammadi, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Fault modeling in controllable polarity silicon nanowire circuits. 453-458
Hardware trojan and active implementation attacks
- Prakash Dey, Abhishek Chakraborty, Avishek Adhikari, Debdeep Mukhopadhyay:
Improved practical differential fault analysis of grain-128. 459-464 - Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
A score-based classification method for identifying hardware-trojans at gate-level netlists. 465-470 - Burçin Çakir, Sharad Malik:
Hardware Trojan detection for gate-level ICs using signal correlation based clustering. 471-476
Variability challenges in nanoscale circuits
- XianWei Zhang, Youtao Zhang, Bruce R. Childers, Jun Yang:
Exploiting DRAM restore time variations in deep sub-micron scaling. 477-482 - Zhe Wang, Xuan Wang, Jiang Xu, Xiaowen Wu, Zhehui Wang, Peng Yang, Luan H. K. Duong, Haoran Li, Rafael Kioji Vivas Maeda, Zhifei Wang:
Adaptively tolerate power-gating-induced power/ground noise under process variations. 483-488 - Adam Teman, Georgios Karakonstantis, Robert Giterman, Pascal Andreas Meinerzhagen, Andreas Peter Burg:
Energy versus data integrity trade-offs in embedded high-density logic compatible dynamic memories. 489-494 - Christian Weis, Matthias Jung, Peter Ehses, Cristiano Santos, Pascal Vivet, Sven Goossens, Martijn Koedam, Norbert Wehn:
Retention time measurements and modelling of bit error rates of WIDE I/O DRAM in MPSoCs. 495-500
Emerging technologies for NoCs
- Luan H. K. Duong, Mahdi Nikdast, Jiang Xu, Zhehui Wang, Yvain Thonnart, Sébastien Le Beux, Peng Yang, Xiaowen Wu, Zhifei Wang:
Coherent crosstalk noise analyses in ring-based optical interconnects. 501-506 - Changlin Chen, Marius Enachescu, Sorin Dan Cotofana:
Enabling vertical wormhole switching in 3D NoC-bus hybrid systems. 507-512 - Andrea Mineo, Mohd Shahrizal Rusli, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania, Muhammad N. Marsono:
A closed loop transmitting power self-calibration scheme for energy efficient WiNoC architectures. 513-518
Critical embedded systems
- Timo Feld, Frank Slomka:
Sufficient response time analysis considering dependencies between rate-dependent tasks. 519-524 - Alessandro Biondi, Giorgio C. Buttazzo:
Engine control: task modeling and analysis. 525-530 - Andrea Höller, Nermin Kajtazovic, Tobias Rauter, Kay Römer, Christian Kreiner:
Evaluation of diverse compiling for software-fault detection. 531-536 - Eberle A. Rambo, Rolf Ernst:
Worst-case communication time analysis of networks-on-chip with shared virtual channels. 537-542
Analyzing and improving memories
- Charalampos Antoniadis, Georgios Karakonstantis, Nestor E. Evmorfopoulos, Andreas Peter Burg, George I. Stamoulis:
On the statistical memory architecture exploration and optimization. 543-548 - Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato:
ECRIPSE: an efficient method for calculating RTN-induced failure probability of an SRAM cell. 549-554 - Jung-Hoon Kim, Sang-Hoon Kim, Jin-Soo Kim:
Subpage programming for extending the lifetime of NAND flash memory. 555-560
Architectures and design for cyber-physical systems
- Nikunj Bajaj, Pierluigi Nuzzo, Michael Masin, Alberto L. Sangiovanni-Vincentelli:
Optimized selection of reliable and cost-effective cyber-physical system architectures. 561-566 - Mengying Zhao, Qing'an Li, Mimi Xie, Yongpan Liu, Jingtong Hu, Chun Jason Xue:
Software assisted non-volatile register reduction for energy harvesting based cyber-physical system. 567-572 - Umar Waqas, Marc Geilen, Jack Kandelaars, Lou J. Somers, Twan Basten, Sander Stuijk, Patrick Vestjens, Henk Corporaal:
A re-entrant flowshop heuristic for online scheduling of the paper path in a large scale printer. 573-578 - Daniel Münch, Michael Paulitsch, Oliver Hanka, Andreas Herkersdorf:
MPIOV: scaling hardware-based I/O virtualization for mixed-criticality embedded real-time systems using non transparent bridges to (multi-core) multi-processor systems. 579-584
Interactive presentations
- Panasayya Yalla, Ekawat Homsirikamol, Jens-Peter Kaps:
Comparison of multi-purpose cores of Keccak and AES. 585-588 - Rafal Baranowski, Farshad Firouzi, Saman Kiamehr, Chang Liu, Mehdi Baradaran Tahoori, Hans-Joachim Wunderlich:
On-line prediction of NBTI-induced aging rates. 589-592 - Jiachao Deng, Yuntan Fang, Zidong Du, Ying Wang, Huawei Li, Olivier Temam, Paolo Ienne, David Novo, Xiaowei Li, Yunji Chen, Chengyong Wu:
Retraining-based timing error mitigation for hardware neural networks. 593-596 - T. Berkin Cilingiroglu, Mahmoud Zangeneh, Aydan Uyar, W. Clem Karl, Janusz Konrad, Ajay Joshi, Bennett B. Goldberg, M. Selim Ünlü:
Dictionary-based sparse representation for resolution improvement in laser voltage imaging of CMOS integrated circuits. 597-600 - Philipp Jovanovic, Ilia Polian:
Fault-based attacks on the Bel-T block cipher family. 601-604 - Rong Ye, Feng Yuan, Jie Zhang, Qiang Xu:
On the premises and prospects of timing speculation. 605-608 - Ioannis Karageorgos, Michele Stucchi, Praveen Raghavan, Julien Ryckaert, Zsolt Tokei, Diederik Verkest, Rogier Baert, Sushil Sakhare, Wim Dehaene:
Impact of interconnect multiple-patterning variability on SRAMs. 609-612 - Anouk Van Laer, Chamath Ellawala, Muhammad Ridwan Madarbux, Philip M. Watts, Timothy M. Jones:
Coherence based message prediction for optically interconnected chip multiprocessors. 613-616 - Roberto Vargas, Eduardo Quiñones, Andrea Marongiu:
OpenMP and timing predictability: a possible union? 617-620 - Georg Macher, Harald Sporer, Reinhard Berlach, Eric Armengaud, Christian Kreiner:
SAHARA: a security-aware hazard and risk analysis method. 621-624 - Santanu Sarma, Nikil D. Dutt, Puneet Gupta, Nalini Venkatasubramanian, Alexandru Nicolau:
Cyberphysical-system-on-chip (CPSoC): a self-aware MPSoC paradigm with cross-layer virtual sensing and actuation. 625-628 - Andrea Corna, L. Fontana, A. A. Nacci, Donatella Sciuto:
Occupancy detection via iBeacon on Android devices for smart building management. 629-632 - Jason Kane, Qing Yang, Robert Hernandez, Willard Simoneau, Matthew Seaton:
A neural machine interface architecture for real-time artificial lower limb control. 633-636
Special day hot topic: platforms for the IoT
- Jan M. Rabaey:
The human intranet: where swarms and humans meet. 637-640
Physical unclonable functions
- Phuong Ha Nguyen, Durga Prasad Sahoo, Rajat Subhra Chakraborty, Debdeep Mukhopadhyay:
Efficient attacks on robust ring oscillator PUF with enhanced challenge-response set. 641-646 - Maryam S. Hashemian, Bhanu Pratap Singh, Francis G. Wolff, Daniel J. Weyer, Steve Clay, Christos A. Papachristou:
A robust authentication methodology using physically unclonable functions in DRAM arrays. 647-652 - Arunkumar Vijayakumar, Sandip Kundu:
A novel modeling attack resistant PUF design based on non-linear voltage transfer characteristics. 653-658
Emerging low power techniques
- A. Arun Goud, Rangharajan Venkatesan, Anand Raghunathan, Kaushik Roy:
Asymmetric underlapped FinFET based robust SRAM design at 7nm node. 659-664 - Arnab Raha, Swagath Venkataramani, Vijay Raghunathan, Anand Raghunathan:
Quality configurable reduce-and-rank for energy efficient approximate computing. 665-670 - Hossein Mamaghanian, Pierre Vandergheynst:
Ultra-low-power ECG front-end design based on compressed sensing. 671-676 - Tony Casagrande, Nagarajan Ranganathan:
GTFUZZ: a novel algorithm for robust dynamic power optimization via gate sizing with fuzzy games. 677-682
Bridging the Moore's law gap with application-specific architectures
- Francesco Conti, Luca Benini:
A ultra-low-energy convolution engine for fast brain-inspired vision in multicore clusters. 683-688 - Bin Wang, Zhuo Liu, Xinning Wang, Weikuan Yu:
Eliminating intra-warp conflict misses in GPU. 689-694 - Fengbin Tu, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei:
RNA: a reconfigurable architecture for hardware neural acceleration. 695-700 - Qian Zhang, Ting Wang, Ye Tian, Feng Yuan, Qiang Xu:
ApproxANN: an approximate computing framework for artificial neural network. 701-706
Multimedia and consumer electronics
- Michael Schaffner, Frank K. Gürkaynak, Aljoscha Smolic, Luca Benini:
DRAM or no-DRAM?: exploring linear solver architectures for image domain warping in 28 nm CMOS. 707-712 - Mungyu Son, Sungkwang Lee, Kyungho Kim, Sungjoo Yoo, Sunggu Lee:
A small non-volatile write buffer to reduce storage writes in smartphones. 713-718 - Shih-Lun Huang, Sheng-Yi Hung, Chung-Ping Chen:
Clustering-based multi-touch algorithm framework for the tracking problem with a large number of points. 719-724 - Ercan Kalali, Ilker Hamzaoglu:
A low energy 2D adaptive median filter hardware. 725-729
Application-mapping strategies for many-cores
- Sebastian Kobbe, Lars Bauer, Jörg Henkel:
Adaptive on-the-fly application performance modeling for many cores. 730-735 - Edoardo Paone, Francesco Robino, Gianluca Palermo, Vittorio Zaccaria, Ingo Sander, Cristina Silvano:
Customization of OpenCL applications for efficient task mapping under heterogeneous platform constraints. 736-741 - Tushar Rawat, Aviral Shrivastava:
Enabling multi-threaded applications on hybrid shared memory manycore architectures. 742-747
Hot topic - trading accuracy for efficient computing
- Swagath Venkataramani, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan:
Computing approximately, and efficiently. 748-751 - Guru Prakash Arumugam, Prashanth Srikanthan, John Augustine, Krishna V. Palem, Eli Upfal, Ayush Bhargava, Parishkrati, Sreelatha Yenugula:
Novel inexact memory aware algorithm co-design for energy efficient computation: algorithmic principles. 752-757 - Shyamsundar Venkataraman, Akash Kumar, Jeremy Schlachter, Christian C. Enz:
Designing inexact systems efficiently using elimination heuristics. 758-763 - Peter D. Düben, Jeremy Schlachter, Parishkrati, Sreelatha Yenugula, John Augustine, Christian C. Enz, Krishna V. Palem, Tim N. Palmer:
Opportunities for energy efficient computing: a study of inexact general purpose processors for high-performance and big-data applications. 764-769
Hot topic - advances in hardware trojans detection
- Julien Francq, Florian Frick:
Introduction to hardware trojan detection methods. 770-775 - Sophie Dupuis, Papa-Sidi Ba, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre:
New testing procedure for finding insertion sites of stealthy hardware trojans. 776-781 - Xuan Thuy Ngo, Ingrid Exurville, Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Zakaria Najm, Jean-Baptiste Rigaud, Bruno Robisson:
Hardware trojan detection by delay and electromagnetic measurements. 782-787 - Franck Courbon, Philippe Loubet-Moundi, Jacques J. A. Fournier, Assia Tria:
A high efficiency hardware trojan detection technique based on fast SEM imaging. 788-793
Routing advances for fault-tolerant and multicast NoCs
- Ammar Karkar, Kin-Fai Tong, Terrence S. T. Mak, Alexandre Yakovlev:
Mixed wire and surface-wave communication fabrics for decentralized on-chip multicasting. 794-799 - Rimpy Bishnoi, Vijay Laxmi, Manoj Singh Gaur, José Flich:
d2-LBDR: distance-driven routing to handle permanent failures in 2D mesh NOCs. 800-805 - Marco Balboni, José Flich, Davide Bertozzi:
Synergistic use of multiple on-chip networks for ultra-low latency and scalable distributed routing reconfiguration. 806-811
System reliability: from runtime to design languages
- Amir Yazdanbakhsh, Divya Mahajan, Bradley Thwaites, Jongse Park, Anandhavel Nagendrakumar, Sindhuja Sethuraman, Kartik Ramkrishnan, Nishanthi Ravindran, Rudra Jariwala, Abbas Rahimi, Hadi Esmaeilzadeh, Kia Bazargan:
Axilog: language support for approximate hardware design. 812-817 - Laura A. Rozo Duque, Jose Manuel Monsalve Diaz, Chengmo Yang:
Improving MPSoC reliability through adapting runtime task schedule based on time-correlated fault behavior. 818-823 - Florian Kriebel, Semeen Rehman, Duo Sun, Pau Vilimelis Aceituno, Muhammad Shafique, Jörg Henkel:
ACSEM: accuracy-configurable fast soft error masking analysis in combinatorial circuits. 824-829 - Qiushi Han, Ming Fan, Linwei Niu, Gang Quan:
Energy minimization for fault tolerant scheduling of periodic fixed-priority applications on multiprocessor platforms. 830-835
Test power and 3-D fault tolerance
- Satya Trinadh, Ch. Sobhan Babu, Shiv Govind Singh, Seetal Potluri, V. Kamakoti:
DP-fill: a dynamic programming approach to X-filling for minimizing peak test power in scan tests. 836-841 - Nan Li, Elena Dubrova, Gunnar Carlsson:
A scan partitioning algorithm for reducing capture power of delay-fault LBIST. 842-847 - Wei-Hen Lo, Kang Chi, TingTing Hwang:
Architecture of ring-based redundant TSV for clustered faults. 848-853
Energy-efficient computing
- Pai-Yu Chen, Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu:
Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip. 854-859 - Tianqi Tang, Lixue Xia, Boxun Li, Rong Luo, Yiran Chen, Yu Wang, Huazhong Yang:
Spiking neural network with RRAM: can we use it for real-world application? 860-865 - Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara:
Comparative study of power-gating architectures for nonvolatile FinFET-SRAM using spintronics-based retention technology. 866-871
Interactive presentations
- Elena-Ioana Vatajelu, Giorgio Di Natale, Marco Indaco, Paolo Prinetto:
STT MRAM-Based PUFs. 872-875 - Johannes Maximilian Kühn, Dustin Peterson, Hideharu Amano, Oliver Bringmann, Wolfgang Rosenstiel:
Spatial and temporal granularity limits of body biasing in UTBB-FDSOI. 876-879 - Yuan Ji, Feng Ran, Cong Ma, David J. Lilja:
A hardware implementation of a radial basis function neural network using stochastic logic. 880-883 - Chao Wang, Xi Li, Xuehai Zhou:
SODA: software defined FPGA based accelerators for big data. 884-887 - Liang Tang, Jude Angelo Ambrose, Akash Kumar, Sri Parameswaran:
Dynamic reconfigurable puncturing for secure wireless communication. 888-891 - Jochen Rust, Frank Ludwig, Steffen Paul:
QR-decomposition architecture based on two-variable numeric function approximation. 892-895 - Saeed Ur Reehman, Cyrille Chavet, Philippe Coussy, Awais Sani:
In-place memory mapping approach for optimized parallel hardware interleaver architectures. 896-899 - Chenchen Fu, Yingchao Zhao, Minming Li, Chun Jason Xue:
Maximizing common idle time on multi-core processors with shared memory. 900-903 - Qiao Li, Liang Shi, Congming Gao, Kaijie Wu, Chun Jason Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha:
Maximizing IO performance via conflict reduction for flash memory storage systems. 904-907 - Abbas Mazloumi, Mehdi Modarressi:
A hybrid packet/circuit-switched router to accelerate memory access in NoC-based chip multiprocessors. 908-911 - Julius von Rosen, Markus Meissner, Lars Hedrich:
Semiautomatic implementation of a bioinspired reliable analog task distribution architecture for multiple analog cores. 912-915 - Muhammad Usman Karim Khan, Muhammad Shafique, Jörg Henkel:
Power-efficient accelerator allocation in adaptive dark silicon many-core systems. 916-919 - Davide Pagano, Mikel Vuka, Marco Rabozzi, Riccardo Cattaneo, Donatella Sciuto, Marco D. Santambrogio:
Thermal-aware floorplanning for partially-reconfigurable FPGA-based systems. 920-923 - Shi-Yu Huang, Meng-Ting Tsai, Kun-Han Hans Tsai, Wu-Tung Cheng:
Feedback-bus oscillation ring: a general architecture for delay characterization and test of interconnects. 924-927 - Vehbi Calayir, Mohamed Darwish, Jeffrey A. Weldon, Larry T. Pileggi:
Analog neuromorphic computing enabled by multi-gate programmable resistive devices. 928-931 - Yuhao Wang, Hantao Huang, Leibin Ni, Hao Yu, Mei Yan, Chuliang Weng, Wei Yang, Junfeng Zhao:
An energy-efficient non-volatile in-memory accelerator for sparse-representation based face recognition. 932-935
Flash memories & numerical approximation
- Han-Yi Lin, Jen-Wei Hsieh:
HLC: software-based half-level-cell flash memory. 936-941 - Ebrahim M. Songhori, Azalia Mirhoseini, Xuyang Lu, Farinaz Koushanfar:
AHEAD: automated framework for hardware accelerated iterative data analysis. 942-947 - Jochen Rust, Steffen Paul:
Design method for multiplier-less two-variable numeric function approximation. 948-953
Dynamic thermal management for multi-cores
- Mehdi Kamal, Arman Iranfar, Ali Afzali-Kusha, Massoud Pedram:
A thermal stress-aware algorithm for power and temperature management of MPSoCs. 954-959 - Gaurav Singla, Gurinderjit Kaur, Ali K. Unver, Ümit Y. Ogras:
Predictive dynamic thermal and power management for heterogeneous mobile platforms. 960-965 - Mohammad Javad Dousti, Massoud Pedram:
Power-efficient control of thermoelectric coolers considering distributed hot spots. 966-971
Industrial system design opportunities
- Sangjo Lee, Joonho Song, Wonchang Lee, Doo Hyun Kim, Jaehyun Kim, Shihwa Lee:
DSP based programmable FHD HEVC decoder. 972-973 - Hoang Anh Du Nguyen, Zaid Al-Ars, Georgios Smaragdos, Christos Strydis:
Accelerating complex brain-model simulations on GPU platforms. 974-979 - Runan Ma, Zhida Hui, Axel Jantsch:
A packet-switched interconnect for many-core systems with BE and RT service. 980-983 - Serge Vladimir Emteu Tchagou, Alexandre Termier, Jean-François Méhaut, Brice Videau, Miguel Santana, René Quiniou:
Reducing trace size in multimedia applications endurance tests. 984-985 - Jean-Marc Philippe, Alexandre Carbon, Olivier Brousse, Michel Paindavoine:
Exploration and design of embedded systems including neural algorithms. 986-991 - Francesco Gavino Brundu, Edoardo Patti, Andrea Acquaviva, Michelangelo Grosso, Gaetano Rasconà, Salvatore Rinaudo, Enrico Macii:
A new distributed framework for integration of district energy data from heterogeneous devices. 992-993
Hot topic - spintronics based computing
- Nicolas Locatelli, Adrien F. Vincent, Alice Mizrahi, Joseph S. Friedman, Damir Vodenicarevic, Joo-Von Kim, Jacques-Olivier Klein, Weisheng Zhao, Julie Grollier, Damien Querlioz:
Spintronic devices as key elements for energy-efficient neuroinspired architectures. 994-999 - Yaojun Zhang, Bonan Yan, Wenqing Wu, Hai Li, Yiran Chen:
Giant spin hall effect (GSHE) logic design for low power application. 1000-1005 - Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Shoun Matsunaga, Masanori Natsui, Akira Mochizuki:
Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm. 1006-1011 - Sophiane Senni, Raphael Martins Brum, Lionel Torres, Gilles Sassatelli, Abdoulaye Gamatié, Bruno Mussard:
Potential applications based on NVM emerging technologies. 1012-1017 - Guangyu Sun, Chao Zhang, Hehe Li, Yue Zhang, Weiqi Zhang, Yizi Gu, Yinan Sun, Jacques-Olivier Klein, Dafine Ravelosona, Yongpan Liu, Weisheng Zhao, Huazhong Yang:
From device to system: cross-layer design exploration of racetrack memory. 1018-1023
Statistical answers to analog/mixed signal design and test problems
- Chenlei Fang, Qicheng Huang, Fan Yang, Xuan Zeng, Xin Li, Chenjie Gu:
Efficient bit error rate estimation for high-speed link by Bayesian model fusion. 1024-1029 - John Liaperdos, Haralampos-G. D. Stratigopoulos, Louay Abdallah, Yiorgos Tsiatouhas, Angela Arapoyanni, Xin Li:
Fast deployment of alternate analog test using Bayesian model fusion. 1030-1035 - Markus Dobler, Manuel Harrant, Monica Rafaila, Georg Pelz, Wolfgang Rosenstiel, Martin Bogdan:
Bordersearch: an adaptive identification of failure regions. 1036-1041 - Hugo R. Gonçalves, Xin Li, Miguel V. Correia, Vítor Tavares, John M. Carulli Jr., Kenneth M. Butler:
A fast spatial variation modeling algorithm for efficient test cost reduction of analog/RF circuits. 1042-1047
Compilers and tools for performance
- Hyeong-Seok Oh, Ji Hwan Yeo, Soo-Mook Moon:
Bytecode-to-C ahead-of-time compilation for Android Dalvik virtual machine. 1048-1053 - Nikolaos Kyrtatas, Daniele G. Spampinato, Markus Püschel:
A basic linear algebra compiler for embedded processors. 1054-1059 - Nishit Ashok Kapadia, Sudeep Pasricha:
VARSHA: variation and reliability-aware application scheduling with adaptive parallelism in the dark-silicon era. 1060-1065
Hot topic - transparent use of accelerators in heterogeneous computing systems
- Nuno Miguel Cardanha Paulino, João Canas Ferreira, João Bispo, João M. P. Cardoso:
Transparent acceleration of program execution using reconfigurable hardware. 1066-1071 - Heiner Giefers, Raphael Polig, Christoph Hagleitner:
Accelerating arithmetic kernels with coherent attached FPGA coprocessors. 1072-1077 - Marvin Damschen, Heinrich Riebler, Gavin Vaz, Christian Plessl:
Transparent offloading of computational hotspots from binary code to Xeon Phi. 1078-1083 - David B. Thomas, Shane T. Fleming, George A. Constantinides, Dan R. Ghica:
Transparent linking of compiled software and synthesized hardware. 1084-1089
NoC optimization
- Anastasios Psarras, I. Seitanidis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
PhaseNoC: TDM scheduling at the virtual-channel level for efficient network traffic isolation. 1090-1095 - Mario R. Casu, Paolo Giaccone:
Rate-based vs delay-based control for DVFS in NoC. 1096-1101 - Turbo Majumder, Xian Li, Paul Bogdan, Partha Pratim Pande:
NoC-enabled multicore architectures for stochastic analysis of biomolecular reactions. 1102-1107
Advanced trends in alternative technologies
- Muhammad Ahsan, Jungsang Kim:
Optimization of quantum computer architecture using a resource-performance simulator. 1108-1113 - Chi-Mei Huang, Chia-Hung Liu, Juinn-Dar Huang:
Volume-oriented sample preparation for reactant minimization on flow-based microfluidic biochips with multi-segment mixers. 1114-1119 - Hui Li, Alain Fourmigue, Sébastien Le Beux, Xavier Letartre, Ian O'Connor, Gabriela Nicolescu:
Thermal aware design method for VCSEL-based on-chip optical interconnect. 1120-1125
Modeling and simulation of extra-functional properties
- Dongwook Lee, Lizy K. John, Andreas Gerstlauer:
Dynamic power and performance back-annotation for fast and accurate functional hardware simulation. 1126-1131 - Roeland Douma, Sebastian Altmeyer, Andy D. Pimentel:
Fast and precise cache performance estimation for out-of-order execution. 1132-1137 - Devendra Rai, Lothar Thiele:
A calibration based thermal modeling technique for complex multicore systems. 1138-1143
Design, synthesis and validation of analog circuits
- Fanshu Jiao, Sergio Montano, Alex Doboli:
Knowledge-intensive, causal reasoning for analog circuit topology synthesis in emergent and innovative applications. 1144-1149 - Behnam Sedighi, Indranil Palit, Xiaobo Sharon Hu, Joseph Nahas, Michael T. Niemier:
A CNN-inspired mixed signal processor based on tunnel transistors. 1150-1155 - Nuno Lourenço, Ricardo Martins, Nuno Horta:
Layout-aware sizing of analog ICs using floorplan & routing estimates for parasitic extraction. 1156-1161 - Hans Georg Brachtendorf, Kai Bittner:
Initial transient response of oscillators with long settling time. 1162-1167
Test generation, fault simulation and diagnosis
- David Lin, Eswaran S, Sharad Kumar, Eric Rentschler, Subhasish Mitra:
Quick error detection tests with fast runtimes for effective post-silicon validation and debug. 1168-1173 - Eric Schneider, Stefan Holst, Michael A. Kochte, Xiaoqing Wen, Hans-Joachim Wunderlich:
GPU-accelerated small delay fault simulation. 1174-1179 - Maksim Gorev, Raimund Ubar, Sergei Devadze:
Fault simulation with parallel exact critical path tracing in multiple core environment. 1180-1185 - Andreas Riefert, Riccardo Cantoro, Matthias Sauer, Matteo Sonza Reorda, Bernd Becker:
On the automatic generation of SBST test programs for in-field test. 1186-1191
Hot topic - monolithic 3D: a path to real 3D integrated chips
- Olivier Billoint, Hossam Sarhan, Iyad Rayane, Maud Vinet, Perrine Batude, Claire Fenouillet-Béranger, Olivier Rozeau, Gerald Cibrario, Fabien Deprat, A. Fustier, Julien Michallet, Olivier Faynot, Ogun Turkyilmaz, Jean-Frédéric Christmann, Sébastien Thuries, Fabien Clermidy:
A comprehensive study of monolithic 3D cell on cell design using commercial 2D tool. 1192-1196 - Max M. Shulaker, Tony F. Wu, Mohamed M. Sabry, Hai Wei, H.-S. Philip Wong, Subhasish Mitra:
Monolithic 3D integration: a path from concept to reality. 1197-1202 - Pierre-Emmanuel Gaillardon, Xifan Tang, Jury Sandrini, Maxime Thammasack, Somayyeh Rahimian Omam, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli:
A ultra-low-power FPGA based on monolithically integrated RRAMs. 1203-1208
Interactive presentations
- Fu-Hsin Chen, Ming-Chang Yang, Yuan-Hao Chang, Tei-Wei Kuo:
PWL: a progressive wear leveling to minimize data migration overheads for nand flash devices. 1209-1212 - Xiaotong Cui, Minhui Zou, Liang Shi, Kaijie Wu:
Towards trustable storage using SSDs with proprietary FTL. 1213-1216 - Begum Egilmez, Gokhan Memik, Seda Ogrenci Memik, Oguz Ergin:
User-specific skin temperature-aware DVFS for smartphones. 1217-1220 - Shafaq Iqtedar, Osman Hasan, Muhammad Shafique, Jörg Henkel:
Formal probabilistic analysis of distributed dynamic thermal management. 1221-1224 - Engin Afacan, Gönenç Berkol, Ali Emre Pusane, Günhan Dündar, I. Faik Baskaya:
A hybrid Quasi Monte Carlo method for yield aware analog circuit sizing tool. 1225-1228 - Manuel J. Barragán, Gildas Léger:
Feature selection for alternate test using wrappers: application to an RF LNA case study. 1229-1232 - Sheng-Yu Fu, Jan-Jan Wu, Wei-Chung Hsu:
Improving SIMD code generation in QEMU. 1233-1236 - Christakis Lezos, Grigoris Dimitroulakos, Konstantinos Masselos:
Reuse distance analysis for locality optimization in loop-dominated applications. 1237-1240 - Di Zhu, Lizhong Chen, Timothy Mark Pinkston, Massoud Pedram:
TAPP: temperature-aware application mapping for NoC-based many-core processors. 1241-1244 - Haseeb Bokhari, Haris Javaid, Muhammad Shafique, Jörg Henkel, Sri Parameswaran:
Malleable NoC: dark silicon inspired adaptable Network-on-Chip. 1245-1248 - Sebastian Steinhorst, Martin Lukasiewycz:
Topology identification for smart cells in modular batteries. 1249-1252 - Ruping Cao, Julien Billoudet, John Ferguson, Lionel Couder, John Cayo, Alexandre Arriordaz, Ian O'Connor:
LVS check for photonic integrated circuits: curvilinear feature extraction and validation. 1253-1256 - Alok Lele, Orlando Moreira, Kees van Berkel:
FP-scheduling for mode-controlled dataflow: a case study. 1257-1260 - Felix Salfelder, Lars Hedrich:
Ageing simulation of analogue circuits and systems using adaptive transient evaluation. 1261-1264 - Stefano Brenna, Andrea Bonetti, Andrea Bonfanti, Andrea L. Lacaita:
A tool for the assisted design of charge redistribution SAR ADCs. 1265-1268 - Michael Zwerger, Helmut E. Graeb:
Detection of asymmetric aging-critical voltage conditions in analog power-down mode. 1269-1272 - José C. García, Juan A. Montiel-Nelson, Javier Sosa, Saeid Nooshabadi:
High performance single supply CMOS inverter level up shifter for multi: supply voltages domains. 1273-1276 - Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda:
Exploring the impact of functional test programs re-used for power-aware testing. 1277-1280 - Hsin-Chen Chen, Cheng-Rong Wu, Katherine Shu-Min Li, Kuen-Jong Lee:
A breakpoint-based silicon debug technique with cycle-granularity for handshake-based SoC. 1281-1284 - Subhadip Kundu, Parthajit Bhattacharya, Rohit Kapur:
Fault diagnosis in designs with extreme low pin test data compressors. 1285-1288 - Charlie Shucheng Zhu, Sharad Malik:
Optimizing dynamic trace signal selection using machine learning and linear programming. 1289-1292
Special day hot topic: wearable medical applications
- Rebecca Baldwin, Stan Bobovych, Ryan W. Robucci, Chintan Patel, Nilanjan Banerjee:
Gait analysis for fall prediction using hierarchical textile-based capacitive sensor arrays. 1293-1298
Emerging memory architectures
- Miguel Angel Lastras-Montaño, Amirali Ghofrani, Kwang-Ting Cheng:
HReRAM: a hybrid reconfigurable resistive random-access memory. 1299-1304 - Kan Zhong, Duo Liu, Linbo Long, Xiao Zhu, Weichen Liu, Qingfeng Zhuge, Edwin Hsing-Mean Sha:
nCode: limiting harmful writes to emerging mobile NVRAM through code swapping. 1305-1310 - Manu Perumkunnil Komalan, Christian Tenllado, José Ignacio Gómez Pérez, Francisco Tirado Fernández, Francky Catthoor:
System level exploration of a STT-MRAM based level 1 data-cache. 1311-1316 - Erfan Azarkhish, Davide Rossi, Igor Loi, Luca Benini:
High performance AXI-4.0 based interconnect for extensible smart memory cubes. 1317-1322
Modern architectures for real-time systems
- Sanjoy K. Baruah:
The federated scheduling of constrained-deadline sporadic DAG task systems. 1323-1328 - Pengcheng Huang, Pratyush Kumar, Georgia Giannopoulou, Lothar Thiele:
Run and be safe: mixed-criticality scheduling with temporary processor speedup. 1329-1334 - Tianyi Wang, Linwei Niu, Shaolei Ren, Gang Quan:
Multi-core fixed-priority scheduling of real-time tasks with statistical deadline guarantee. 1335-1340
Energy aware data center: design and management
- Eunhyeok Park, Junwhan Ahn, Sungpack Hong, Sungjoo Yoo, Sunggu Lee:
Memory fast-forward: a low cost special function unit to enhance energy efficiency in GPU for big data processing. 1341-1346 - Shuo Liu, Soamar Homsi, Ming Fan, Shaolei Ren, Gang Quan, Shangping Ren:
Power minimization for data center with guaranteed QoS. 1347-1352 - Christian Conficoni, Andrea Bartolini, Andrea Tilli, Giampietro Tecchiolli, Luca Benini:
Energy-aware cooling for hot-water cooled supercomputers. 1353-1358
Reconfigurable architectures and applications
- Alexandru Gheolbanoiu, Lucian Petrica, Sorin Cotofana:
Hybrid adaptive clock management for FPGA processor acceleration. 1359-1364 - Chunan Wei, Ashutosh Dhar, Deming Chen:
A scalable and high-density FPGA architecture with multi-level phase change memory. 1365-1370 - Anand Ramachandran, Yun Heo, Wen-mei W. Hwu, Jian Ma, Deming Chen:
FPGA accelerated DNA error correction. 1371-1376
Circuit design and test: from characterization to measurement
- Seyed Nematollah Ahmadyan, Chenjie Gu, Suriyaprakash Natarajan, Eli Chiprout, Shobha Vasudevan:
Fast eye diagram analysis for high-speed CMOS circuits. 1377-1382 - Li Yu, Sharad Saxena, Christopher Hess, Ibrahim M. Elfadel, Dimitri A. Antoniadis, Duane S. Boning:
Statistical library characterization using belief propagation across multiple technology nodes. 1383-1388 - Gildas Léger:
Combining adaptive alternate test and multi-site. 1389-1394 - John Liaperdos, Angela Arapoyanni, Yiorgos Tsiatouhas:
A method for the estimation of defect detection probability of analog/RF defect-oriented tests. 1395-1400
Expanding the applicability of formal methods
- Ryan Berryhill, Andreas G. Veneris:
Automated rectification methodologies to functional state-space unreachability. 1401-1406 - Priyanka Darke, Bharti Chimdyalwar, R. Venkatesh, Ulka Shrotri, Ravindra Metta:
Over-approximating loops to prove properties using bounded model checking. 1407-1412 - Sebastiaan J. C. Joosten, Julien Schmaltz:
Automatic extraction of micro-architectural models of communication fabrics from register transfer level designs. 1413-1418 - Frank P. Burns, Danil Sokolov, Alexandre Yakovlev:
GALS synthesis and verification for xMAS models. 1419-1424
Variability and robustness for emerging technologies
- Haitong Li, Zizhen Jiang, Peng Huang, Y. Wu, Hong-Yu Chen, Bin Gao, Xiaoyan Liu, Jinfeng Kang, H.-S. Philip Wong:
Variation-aware, reliability-emphasized design and optimization of RRAM using SPICE model. 1425-1430 - Seyedhamidreza Motaman, Swaroop Ghosh, Nitin Rathi:
Impact of process-variations in STTRAM and adaptive boosting for robustness. 1431-1436 - Zoha Pajouhi, Xuanyao Fong, Kaushik Roy:
Device/circuit/architecture co-design of reliable STT-MRAM. 1437-1442 - Ankit Sharma, A. Arun Goud, Kaushik Roy:
Sub-10 nm FinFETs and Tunnel-FETs: from devices to systems. 1443-1448
Logic synthesis: the faithful, the approximate and the stochastic
- Junjun Hu, Weikang Qian:
A new approximate adder with low relative error and correct sign calculation. 1449-1454 - Matthias Függer, Robert Najvirt, Thomas Nowak, Ulrich Schmid:
Towards binary circuit models that faithfully capture physical solvability. 1455-1460 - Yi Diao, Tak-Kei Lam, Xing Wei, Yu-Liang Wu:
A coupling area reduction technique applying ODC shifting. 1461-1466 - Zheng Zhao, Weikang Qian:
A general design of stochastic circuit and its synthesis. 1467-1472
Ultra-low power devices for health and rehabilitation
- Leonardo Guardati, Filippo Casamassima, Elisabetta Farella, Luca Benini:
Paper, pen and ink: an innovative system and software framework to assist writing rehabilitation. 1473-1478 - Masoud Shahshahani Amirhossein, Paolo Motto Ros, Alberto Bonanno, Marco Crepaldi, Maurizio Martina, Danilo Demarchi, Guido Masera:
An all-digital spike-based ultra-low-power IR-UWB dynamic average threshold crossing scheme for muscle force wireless transmission. 1479-1484 - Shahzad Muzaffar, Jerald Yoo, Ayman Shabra, Ibrahim Abe M. Elfadel:
A pulsed-index technique for single-channel, low-power, dynamic signaling. 1485-1490
Video architectures for multimedia and communications
- Swagath Venkataramani, Victor Bahl, Xian-Sheng Hua, Jie Liu, Jin Li, Matthai Philipose, Bodhi Priyantha, Mohammed Shoaib:
SAPPHIRE: an always-on context-aware computer vision system for portable devices. 1491-1496 - Abbas Rahimi, Amirali Ghofrani, Kwang-Ting Cheng, Luca Benini, Rajesh K. Gupta:
Approximate associative memristive memory for energy-efficient GPUs. 1497-1502 - Mi Sun Park, Omesh Tickoo, Vijaykrishnan Narayanan, Mary Jane Irwin, Ravi Iyer:
Platform-aware dynamic configuration support for efficient text processing on heterogeneous system. 1503-1508 - Cláudio Machado Diniz, Muhammad Shafique, Felipe Vogel Dalcin, Sergio Bampi, Jörg Henkel:
A deblocking filter hardware architecture for the high efficiency video coding standard. 1509-1514
Exploiting dark silicon
- Santiago Pagani, Jian-Jia Chen, Muhammad Shafique, Jörg Henkel:
MatEx: efficient transient and peak temperature computation for compact thermal models. 1515-1520 - Zhuo Chen, Diana Marculescu:
Distributed reinforcement learning for power limited many-core system performance optimization. 1521-1526 - Amirhossein Mirhosseini, Mohammad Sadrosadati, Ali Fakhrzadehgan, Mehdi Modarressi, Hamid Sarbazi-Azad:
An energy-efficient virtual channel power-gating mechanism for on-chip networks. 1527-1532 - Young-geun Kim, Minyong Kim, Jae Min Kim, Sung Woo Chung:
M-DTM: migration-based dynamic thermal management for heterogeneous mobile multi-core processors. 1533-1538
Interactive presentations
- Robert Perricone, Yining Zhu, Katherine M. Sanders, Xiaobo Sharon Hu, Michael T. Niemier:
Towards systematic design of 3D pNML layouts. 1539-1542 - Matt Poremba, Sparsh Mittal, Dong Li, Jeffrey S. Vetter, Yuan Xie:
DESTINY: a tool for modeling emerging 3D NVM and eDRAM caches. 1543-1546 - Karim Kanoun, Mihaela van der Schaar:
Big-data streaming applications scheduling with online learning and concept drift detection. 1547-1550 - Christophe Huriaux, Antoine Courtay, Olivier Sentieys:
Design flow and run-time management for compressed FPGA configurations. 1551-1554 - Wael Dghais, Jonathan Rodriguez:
Empirical modelling of FDSOI CMOS inverter for signal/power integrity simulation. 1555-1558 - Osman Emir Erol, Sule Ozev, Chandra K. H. Suresh, Rubin A. Parekhji, Lakshmanan Balasubramanian:
On-chip measurement of bandgap reference voltage using a small form factor VCO based zoom-in ADC. 1559-1562 - Arash Saifhashemi, Hsin-Ho Huang, Priyanka Bhalerao, Peter A. Beerel:
Logical equivalence checking of asynchronous circuits using commercial tools. 1563-1566 - Che-Wei Chang, Rainer Dömer:
May-happen-in-parallel analysis of ESL models using UPPAAL model checking. 1567-1570 - Kumar Madhukar, Mandayam K. Srivas, Björn Wachter, Daniel Kroening, Ravindra Metta:
Verifying synchronous reactive systems using lazy abstraction. 1571-1574 - Rangharajan Venkatesan, Swagath Venkataramani, Xuanyao Fong, Kaushik Roy, Anand Raghunathan:
Spintastic: <u>spin</u>-based s<u>t</u>och<u>astic</u> logic for energy-efficient computing. 1575-1578 - Ji Li, Qing Xie, Yanzhi Wang, Shahin Nazarian, Massoud Pedram:
Leakage power reduction for deeply-scaled FinFET circuits operating in multiple voltage regimes using fine-grained gate-length biasing technique. 1579-1582 - Hong-Yan Su, Chih-Hao Hsu, Yih-Lang Li:
SubHunter: a high-performance and scalable sub-circuit recognition method with Prüfer-encoding. 1583-1586 - Rohit Kumar, Bing Li, Yiren Shen, Ulf Schlichtmann, Jiang Hu:
Timing verification for adaptive integrated circuits. 1587-1590 - Jian Kuang, Wing-Kai Chow, Evangeline F. Y. Young:
A robust approach for process variation aware mask optimization. 1591-1594 - Xingyu Liu, Yangdong Deng, Yufei Ni, Zonghui Li:
FastTree: a hardware KD-tree construction acceleration engine for real-time ray tracing. 1595-1598 - Christian Brugger, Javier Alejandro Varela, Norbert Wehn, Songyin Tang, Ralf Korn:
Reverse longstaff-schwartz american option pricing on hybrid CPU/FPGA systems. 1599-1602 - Mohammad Javad Dousti, Antonio Petraglia, Massoud Pedram:
Accurate electrothermal modeling of thermoelectric generators. 1603-1606 - Qing Xie, Younghyun Kim, Donkyu Baek, Yanzhi Wang, Massoud Pedram, Naehyuck Chang:
Efficiency-driven design time optimization of a hybrid energy storage system with networked charge transfer interconnect. 1607-1610
Special day hot topic: technology and design platforms for diagnostics
- Daniele Bortolotti, Mauro Mangia, Andrea Bartolini, Riccardo Rovatti, Gianluca Setti, Luca Benini:
An ultra-low power dual-mode ECG monitor for healthcare and wellness. 1611-1616
Solver advances and emerging applications
- Karina Gitina, Ralf Wimmer, Sven Reimer, Matthias Sauer, Christoph Scholl, Bernd Becker:
Solving DQBF through quantifier elimination. 1617-1622 - Xiaojun Sun, Priyank Kalla, Tim Pruss, Florian Enescu:
Formal verification of sequential Galois field arithmetic circuits using algebraic geometry. 1623-1628 - Xing Wei, Yi Diao, Tak-Kei Lam, Yu-Liang Wu:
A universal macro block mapping scheme for arithmetic circuits. 1629-1634 - Khaza Anuarul Hoque, Otmane Aït Mohamed, Yvon Savaria:
Towards an accurate reliability, availability and maintainability analysis approach for satellite systems based on probabilistic model checking. 1635-1640
Patterning, pairing, placement and packing
- Zhiqing Liu, Chuangwen Liu, Evangeline F. Y. Young:
An effective triple patterning aware grid-based detailed routing approach. 1641-1646 - Ang Lu, Hsueh-Ju Lu, En-Jang Jang, Yu-Po Lin, Chun-Hsiang Hung, Chun-Chih Chuang, Rung-Bin Lin:
Simultaneous transistor pairing and placement for CMOS standard cells. 1647-1652 - Yu-Min Lee, Chun Chen, JiaXing Song, Kuan-Te Pan:
A TSV noise-aware 3-D placer. 1653-1658 - Woohyun Chung, Seongbo Shim, Youngsoo Shin:
Identifying redundant inter-cell margins and its application to reducing routing congestion. 1659-1664
High-level specifications and models
- Peter Poplavko, Dario Socci, Paraskevas Bourgos, Saddek Bensalem, Marius Bozga:
Models for deterministic execution of real-time multiprocessor applications. 1665-1670 - Liliana Andrade, Torsten Maehne, Alain Vachoux, Cédric Ben Aoun, François Pêcheux, Marie-Minerve Louërat:
Pre-simulation symbolic analysis of synchronization issues between discrete event and timed data flow models of computation. 1671-1676 - Rongjie Yan, Chih-Hong Cheng, Yesheng Chai:
Formal consistency checking over specifications in natural languages. 1677-1682
New perspectives in next-generation medical systems
- Aya Ibrahim, Pascal Hager, Andrea Bartolini, Federico Angiolini, Marcel Arditi, Luca Benini, Giovanni De Micheli:
Tackling the bottleneck of delay tables in 3D ultrasound imaging. 1683-1688 - Benjamin Sporrer, Luca Bettini, Christian Vogt, Andreas Mehmann, Jonas Reber, Josip Marjanovic, David O. Brunner, Thomas Burger, Klaas Paul Pruessmann, Gerhard Tröster, Qiuting Huang:
Integrated CMOS receiver for wearable coil arrays in MRI applications. 1689-1694 - John R. Farserotu, Jean-Dominique Decotignie, Jacek Baborowski, P.-N. Volpe, C. R. Quirós, Vladimir Kopta, Christian C. Enz, S. Lacour, H. Michaud, R. Martuzzi, Volker M. Koch, H. Huang, T. Li, Christian Antfolk:
Tactile prosthetics in WiseSkin. 1695-1697
Hot topic - the next generation of virtual prototyping: ultra-fast yet accurate simulation of HW/SW systems
- Oliver Bringmann, Wolfgang Ecker, Andreas Gerstlauer, Ajay Goyal, Daniel Mueller-Gritschneder, Prasanth Sasidharan, Simranjit Singh:
The next generation of virtual prototyping: ultra-fast yet accurate simulation of HW/SW systems. 1698-1707
Hot topic - multi/many-core programming: where are we standing?
- Jerónimo Castrillón, Lothar Thiele, Lars Schor, Weihua Sheng, Ben H. H. Juurlink, Mauricio Alvarez-Mesa, Angela Pohl, Ralph Jessenberger, Victor Reyes, Rainer Leupers:
Multi/many-core programming: where are we standing? 1708-1717
Hot topic - memristor based computation-in-memory architecture for data-intensive applications
- Said Hamdioui, Lei Xie, Hoang Anh Du Nguyen, Mottaqiallah Taouil, Koen Bertels, Henk Corporaal, Hailong Jiao, Francky Catthoor, Dirk J. Wouters, Eike Linn, Jan van Lunteren:
Memristor based computation-in-memory architecture for data-intensive applications. 1718-1725
Panel - the future of electronics, semiconductor, and design in Europe
- Marco Casale-Rossi, Giovanni De Micheli, Jalal Bagherli, Thierry Collette, Antun Domic, Horst Symanzik, Hossein Yassaie:
The future of electronics, semiconductors, and design in Europe: panel. 1726-1728
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2026-01-03 00:33 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
