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ORCIDPACT 2000: Philadelphia, Pennsylvania, USA
- Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques (PACT'00), Philadelphia, Pennsylvania, USA, October 15-19, 2000. IEEE Computer Society 2000, ISBN 0-7695-0622-4
Register Allocation and Analysis
- Mikhail Smelyanskiy, Gary S. Tyson, Edward S. Davidson:
Register Queues: A New Hardware/Software Approach to Efficient Software Pipelining. 3-12 - Jason Hiser, Steve Carr
, Philip H. Sweany:
Global Register Partitioning. 13-23 - Tom Way, Ben Breech, Lori L. Pollock:
Region Formation Analysis with Demand-Driven Inlining for Region-Based Optimization. 24-36
Architectural Design
- Jian Liang, Sriram Swaminathan, Russell Tessier:
aSOC: A Scalable, Single-Chip Communications Architecture. 37-46 - Ilanthiraiyan Pragaspathy, Babak Falsafi:
Address Partitioning in DSM Clusters with Parallel Coherence Controllers. 47-56 - Bruce R. Childers, Jack W. Davidson:
Custom Wide Counterflow Pipelines for High-Performance Embedded Applications. 57-70
Optimizations and Opportunities
- Kim M. Hazelwood, Thomas M. Conte:
A Lightweight Algorithm for Dynamic If-Conversion during Dynamic Optimization. 71-80 - Kevin Scott, Jack W. Davidson:
Exploring the Limits of Sub-Word Level Parallelism. 81-91 - Amarildo T. da Costa, Felipe M. G. França, Eliseu M. Chaves Filho:
The Dynamic Trace Memorization Reuse Technique. 92-99 - Jian Huang, David J. Lilja:
Exploring Sub-Block Value Reuse for Superscalar Processors. 100-110
High Performance Memory Techniques
- Jaejin Lee, David A. Padua:
Hiding Relaxed Memory Consistency with Compilers. 111-122 - David M. Koppelman:
Neighborhood Prefetching on Multiprocessors Using Instruction History. 123-132 - Gordon B. Bell, Kevin M. Lepak, Mikko H. Lipasti:
Characterization of Silent Stores. 133-144
Speculation and Prediction
- Sang Jeong Lee, Pen-Chung Yew:
On Some Implementation Issues for Value Prediction on Wide-Issue ILP Processors. 145-156 - Roy Dz-Ching Ju, Kevin Nomura, Uma Mahadevan, Le-Chun Wu:
A Unified Compiler Framework for Control and Data Speculation. 157-168 - Uma Mahadevan, Kevin Nomura, Roy Dz-Ching Ju, Rick Hank:
Applying Data Speculation in Modulo Scheduled Loops. 169-178
Branch Prediction
- Jayanth Gummaraju, Manoj Franklin:
Branch Prediction in Multi-Threaded Processors. 179-188 - Alex Ramírez, Josep Lluís Larriba-Pey, Mateo Valero:
The Effect of Code Reordering on Branch Prediction. 189-198 - Kevin Skadron, Margaret Martonosi, Douglas W. Clark:
A Taxonomy of Branch Mispredictions, and Alloyed Prediction as a Robust Solution to Wrong-History Mispredictions. 199-206 - Jan Hoogerbrugge:
Dynamic Branch Prediction for a VLIW Processor. 207-216
Parallel Computation
- Luís M. B. Lopes, Fernando M. A. Silva, Vasco Thudichum Vasconcelos:
Fine Grained Multithreading with Process Calculi. 217-226 - Mahmut T. Kandemir, J. Ramanujam:
Data Relation Vectors: A New Abstraction for Data Optimizations. 227-236 - Toru Kisuki, Peter M. W. Knijnenburg, Michael F. P. O'Boyle:
Combined Selection of Tile Sizes and Unroll Factors Using Iterative Compilation. 237-248
Applications
- Kang Su Gatlin, Larry Carter:
Faster FFTs via Architecture-Cognizance. 249-260 - Edwin Naroska, Rung-Ji Shang, Feipei Lai, Uwe Schwiegelshohn:
Hybrid Parallel Circuit Simulation Approaches. 261-270 - Martin Schulz:
Multithreaded Programming of PC Clusters. 271-280
Instruction Scheduling
- Hui Wu, Joxan Jaffar, Roland H. C. Yap:
A Fast Algorithm for Scheduling Instructions with Deadline Constraints on RISC Processors. 281-290 - Rainer Leupers:
Instruction Scheduling for Clustered VLIW DSPs. 291-300 - Santosh G. Abraham, Waleed Meleis, Ivan D. Baev:
Efficient Backtracking Instruction Schedulers. 301-308
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