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ORCIDRainer Leupers
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- affiliation: RWTH Aachen University, Germany
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2020 – today
- 2023
[j50]Niraj N. Sharma
, Riya Jain, Mohana Madhumita Pokkuluri, Sachin B. Patkar, Rainer Leupers, Rishiyur S. Nikhil, Farhad Merchant:
CLARINET: A quire-enabled RISC-V-based framework for posit arithmetic empiricism. J. Syst. Archit. 135: 102801 (2023)- [c232]Nils Bosbach, Lukas Jünger, Rebecca Pelke, Niko Zurstraßen, Rainer Leupers:
Entropy-Based Analysis of Benchmarks for Instruction Set Simulators. DroneSE/RAPIDO@HiPEAC 2023: 54-59 - [c231]Lennart M. Reimann, Sarp Erdönmez, Dominik Sisejkovic, Rainer Leupers:
Quantitative Information Flow for Hardware: Advancing the Attack Landscape. LASCAS 2023: 1-4 - [i28]Felix Staudigl, Thorben Fetz, Rebecca Pelke, Dominik Sisejkovic, Jan Moritz Joseph, Leticia Bolzani Poehls, Rainer Leupers:
Fault Injection in Native Logic-in-Memory Computation on Neuromorphic Hardware. CoRR abs/2302.07655 (2023) - [i27]Lennart M. Reimann, Felix Staudigl, Rainer Leupers:
Automated Information Flow Analysis for Integrated Computing-in-Memory Modules. CoRR abs/2304.05682 (2023) - [i26]Elmira Moussavi, Animesh Singh, Dominik Sisejkovic, Aravind Padma Kumar, Daniyar Kizatov, Sven Ingebrandt, Rainer Leupers, Vivek Pachauri, Farhad Merchant:
Gate Camouflaging Using Reconfigurable ISFET-Based Threshold Voltage Defined Logic. CoRR abs/2304.05686 (2023) - 2022
- [j49]Felix Staudigl, Farhad Merchant, Rainer Leupers:
A Survey of Neuromorphic Computing-in-Memory: Architectures, Simulators, and Security. IEEE Des. Test 39(2): 90-99 (2022) - [j48]Niko Zurstraßen, Lukas Jünger, Tim Kogel, Holger Keding, Rainer Leupers:
AMAIX In-Depth: A Generic Analytical Model for Deep Learning Accelerators. Int. J. Parallel Program. 50(2): 295-318 (2022) - [j47]Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Rainer Leupers:
Deceptive Logic Locking for Hardware Integrity Protection Against Machine Learning Attacks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(6): 1716-1729 (2022) - [c230]Felix Staudigl, Karl J. X. Sturm, Maximilian Bartel, Thorben Fetz, Dominik Sisejkovic, Jan Moritz Joseph, Letícia Maria Bolzani Pöhls, Rainer Leupers:
X-Fault: Impact of Faults on Binary Neural Networks in Memristor-Crossbar Arrays with Logic-in-Memory Computation. AICAS 2022: 174-177 - [c229]Dominik Sisejkovic, Luca Collini, Benjamin Tan, Christian Pilato, Ramesh Karri, Rainer Leupers:
Designing ML-resilient locking at register-transfer level. DAC 2022: 769-774 - [c228]Melvin Galicia, Stephan Menzel, Farhad Merchant, Maximilian Müller, Hsin-Yu Chen, Qing-Tai Zhao, Felix Cüppers, Abdur R. Jalil, Qi Shu, Peter Schüffelgen, Gregor Mussler, Carsten Funck, Christian Lanius, Stefan Wiefels, Moritz von Witzleben, Christopher Bengel, Nils Kopperberg, Tobias Ziegler, R. Walied Ahmad, Alexander Krüger, Leticia Pöhls, Regina Dittmann, Susanne Hoffmann-Eifert, Vikas Rana, Detlev Grützmacher, Matthias Wuttig, Dirk J. Wouters, Andrei Vescan, Tobias Gemmeke, Joachim Knoch, Max C. Lemme, Rainer Leupers, Rainer Waser:
NEUROTEC I: Neuro-inspired Artificial Intelligence Technologies for the Electronics of the Future. DATE 2022: 957-962 - [c227]Felix Staudigl, Hazem Al Indari, Daniel Schön, Dominik Sisejkovic, Farhad Merchant, Jan Moritz Joseph, Vikas Rana, Stephan Menzel, Rainer Leupers:
NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories. DATE 2022: 1181-1184 - [c226]Lukas Jünger, Simon Winther, Rainer Leupers:
X-on-X: Distributed Parallel Virtual Platforms for Heterogeneous Systems. DSD 2022: 142-148 - [c225]Yee Yang Tan, Felix Staudigl, Lukas Jünger, Anna Drewes, Rainer Leupers, Jan Moritz Joseph:
EmuNoC: Hybrid Emulation for Fast and Flexible Network-on-Chip Prototyping on FPGAs. FPL 2022: 334-341 - [c224]Elmira Moussavi, Dominik Sisejkovic, Fabian Brings, Daniyar Kizatov, Animesh Singh, Xuan Thang Vu, Rainer Leupers, Sven Ingebrandt, Vivek Pachauri, Farhad Merchant:
pHGen: A pH-Based Key Generation Mechanism Using ISFETs. HOST 2022: 61-64 - [c223]Melvin Galicia, Farhad Merchant, Rainer Leupers:
A Parallel SystemC Virtual Platform for Neuromorphic Architectures. ISQED 2022: 1-6 - [c222]Elmira Moussavi, Dominik Sisejkovic, Animesh Singh, Daniyar Kizatov, Rainer Leupers, Sven Ingebrandt, Vivek Pachauri, Farhad Merchant:
A Temperature Independent Readout Circuit for ISFET-Based Sensor Applications. LATS 2022: 1-4 - [c221]Sebastian Birke, Bjoern Hartmann, Dominik Auras, Markus Wloka, Gerd Ascheid, Rainer Leupers:
Design and Exploration of an ARC-Coprocessor for LSTM Based Audio Applications. NorCAS 2022: 1-7 - [c220]Lukas Jünger, Antonios Salios, Peter Blöcher, Rainer Leupers:
Virtual Platform Acceleration through Userspace Host Execution. SOCC 2022: 1-6 - [c219]Nils Bosbach, Jan Moritz Joseph, Rainer Leupers, Lukas Jünger:
NISTT: A Non-Intrusive SystemC-TLM 2.0 Tracing Tool. VLSI-SoC 2022: 1-6 - [c218]Simranjeet Singh, Srinivasu Bodapati, Sachin B. Patkar, Rainer Leupers, Anupam Chattopadhyay, Farhad Merchant:
PA-PUF: A Novel Priority Arbiter PUF. VLSI-SoC 2022: 1-6 - [i25]Elmira Moussavi, Dominik Sisejkovic, Fabian Brings, Daniyar Kizatov, Animesh Singh, Xuan Thang Vu, Sven Ingebrandt, Rainer Leupers, Vivek Pachauri, Farhad Merchant:
pHGen: A pH-Based Key Generation Mechanism Using ISFETs. CoRR abs/2202.12085 (2022) - [i24]Dominik Sisejkovic, Luca Collini, Benjamin Tan, Christian Pilato, Ramesh Karri, Rainer Leupers:
Designing ML-Resilient Locking at Register-Transfer Level. CoRR abs/2203.05399 (2022) - [i23]Felix Staudigl, Karl J. X. Sturm, Maximilian Bartel, Thorben Fetz, Dominik Sisejkovic, Jan Moritz Joseph, Letícia Maria Bolzani Pöhls, Rainer Leupers:
X-Fault: Impact of Faults on Binary Neural Networks in Memristor-Crossbar Arrays with Logic-in-Memory Computation. CoRR abs/2204.01501 (2022) - [i22]Yee Yang Tan, Felix Staudigl, Lukas Jünger, Anna Drewes, Rainer Leupers, Jan Moritz Joseph:
EmuNoC: Hybrid Emulation for Fast and Flexible Network-on-Chip Prototyping on FPGAs. CoRR abs/2206.11613 (2022) - [i21]Simranjeet Singh, Srinivasu Bodapati, Sachin B. Patkar, Rainer Leupers, Anupam Chattopadhyay, Farhad Merchant:
PA-PUF: A Novel Priority Arbiter PUF. CoRR abs/2207.10526 (2022) - [i20]Nils Bosbach, Lukas Jünger, Jan Moritz Joseph, Rainer Leupers:
NISTT: A Non-Intrusive SystemC-TLM 2.0 Tracing Tool. CoRR abs/2207.11036 (2022) - [i19]Elmira Moussavi, Dominik Sisejkovic, Animesh Singh, Daniyar Kizatov, Rainer Leupers, Sven Ingebrandt, Vivek Pachauri, Farhad Merchant:
A Temperature Independent Readout Circuit for ISFET-Based Sensor Applications. CoRR abs/2208.04769 (2022) - [i18]Lennart M. Reimann, Sarp Erdönmez, Dominik Sisejkovic, Rainer Leupers:
Quantitative Information Flow for Hardware: Advancing the Attack Landscape. CoRR abs/2211.16891 (2022) - 2021
- [j46]Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Harshit Srivastava, Ahmed Hallawa, Rainer Leupers:
Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach. ACM J. Emerg. Technol. Comput. Syst. 17(3): 30:1-30:26 (2021) - [j45]Andreas Bytyn, Rainer Leupers, Gerd Ascheid:
ConvAix: An Application-Specific Instruction-Set Processor for the Efficient Acceleration of CNNs. IEEE Open J. Circuits Syst. 2: 3-15 (2021) - [c217]Jan Moritz Joseph, Lennart Bamberg, Geonhwa Jeong, Ruei-Ting Chien, Rainer Leupers, Alberto García-Ortiz, Tushar Krishna, Thilo Pionteck:
Bridging the Frequency Gap in Heterogeneous 3D SoCs through Technology-Specific NoC Router Architectures. ASP-DAC 2021: 197-203 - [c216]Lukas Jünger, Carmine Bianco, Kristof Niederholtmeyer, Dietmar Petras, Rainer Leupers:
Optimizing Temporal Decoupling using Event Relevance. ASP-DAC 2021: 331-337 - [c215]Ilia Polian, Frank Altmann, Tolga Arul, Christian Boit, Ralf Brederlow, Lucas Davi, Rolf Drechsler, Nan Du, Thomas Eisenbarth, Tim Güneysu, Sascha Hermann, Matthias Hiller, Rainer Leupers, Farhad Merchant, Thomas Mussenbrock, Stefan Katzenbeisser, Akash Kumar, Wolfgang Kunz, Thomas Mikolajick, Vivek Pachauri, Jean-Pierre Seifert, Frank Sill Torres, Jens Trommer:
Nano Security: From Nano-Electronics to Secure Systems. DATE 2021: 1334-1339 - [c214]Milan Copic, Rainer Leupers, Gerd Ascheid:
Runnable Configuration in Mixed Classic/Adaptive AUTOSAR Systems by Leveraging Nondeterminism. DSD 2021: 418-425 - [c213]Lennart M. Reimann, Luca Hanel, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers:
QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog. ICCD 2021: 603-607 - [c212]Jan Moritz Joseph, Ananda Samajdar, Lingjun Zhu, Rainer Leupers, Sung Kyu Lim, Thilo Pionteck, Tushar Krishna:
Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators. ISQED 2021: 60-66 - [c211]Vinay Saxena, Ankitha Reddy, Jonathan Neudorfer, John L. Gustafson, Sangeeth Nambiar, Rainer Leupers, Farhad Merchant:
Brightening the Optical Flow through Posit Arithmetic. ISQED 2021: 463-468 - [c210]Jan Moritz Joseph, Murat Sezgin Baloglu, Yue Pan, Rainer Leupers, Lennart Bamberg:
NEWROMAP: mapping CNNs to NoC-interconnected self-contained data-flow accelerators for edge-AI. NOCS 2021: 15-20 - [c209]Lukas Jünger, Alexander Belke, Rainer Leupers:
Software-defined Temporal Decoupling in Virtual Platforms. SoCC 2021: 40-45 - [c208]Melvin Galicia, Ali BanaGozar, Karl J. X. Sturm, Felix Staudigl, Sander Stuijk, Henk Corporaal, Rainer Leupers:
NeuroVP: A System-Level Virtual Platform for Integration of Neuromorphic Accelerators. SoCC 2021: 236-241 - [c207]Dominik Sisejkovic, Rainer Leupers:
Trustworthy Hardware Design with Logic Locking. VLSI-SoC 2021: 1-2 - [c206]Dominik Sisejkovic, Lennart M. Reimann, Elmira Moussavi, Farhad Merchant, Rainer Leupers:
Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities. VLSI-SoC 2021: 1-6 - [c205]Farhad Merchant, Dominik Sisejkovic, Lennart M. Reimann, Kirthihan Yasotharan, Thomas Grass, Rainer Leupers:
ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework. VLSID 2021: 270-275 - [c204]Ihsen Alouani, Anouar Ben Khalifa, Farhad Merchant, Rainer Leupers:
An Investigation on Inherent Robustness of Posit Data Representation. VLSID 2021: 276-281 - [i17]Ihsen Alouani, Anouar Ben Khalifa, Farhad Merchant, Rainer Leupers:
An Investigation on Inherent Robustness of Posit Data Representation. CoRR abs/2101.01416 (2021) - [i16]Farhad Merchant, Dominik Sisejkovic, Lennart M. Reimann, Kirthihan Yasotharan, Thomas Grass, Rainer Leupers:
ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework. CoRR abs/2101.05591 (2021) - [i15]Vinay Saxena, Ankitha Reddy, Jonathan Neudorfer, John L. Gustafson, Sangeeth Nambiar, Rainer Leupers, Farhad Merchant:
Brightening the Optical Flow through Posit Arithmetic. CoRR abs/2101.06665 (2021) - [i14]Dominik Sisejkovic, Lennart M. Reimann, Elmira Moussavi, Farhad Merchant, Rainer Leupers:
Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities. CoRR abs/2107.01915 (2021) - [i13]Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Rainer Leupers:
Deceptive Logic Locking for Hardware Integrity Protection against Machine Learning Attacks. CoRR abs/2107.08695 (2021) - [i12]Lennart M. Reimann, Luca Hanel, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers:
QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog. CoRR abs/2109.02379 (2021) - [i11]Felix Staudigl, Hazem Al Indari, Daniel Schön, Dominik Sisejkovic, Farhad Merchant, Jan Moritz Joseph, Vikas Rana, Stephan Menzel, Rainer Leupers:
NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories. CoRR abs/2112.01087 (2021) - [i10]Melvin Galicia, Farhad Merchant, Rainer Leupers:
A Parallel SystemC Virtual Platform for Neuromorphic Architectures. CoRR abs/2112.13157 (2021) - 2020
- [j44]Jure Vreca, Karl J. X. Sturm, Ernest Gungl, Farhad Merchant, Paolo Bientinesi, Rainer Leupers, Zmago Brezocnik:
Accelerating Deep Learning Inference in Constrained Embedded Devices Using Hardware Loops and a Dot Product Unit. IEEE Access 8: 165913-165926 (2020) - [j43]Milan Copic, Rainer Leupers, Gerd Ascheid:
Reducing idle time in event-triggered software execution via runnable migration and DPM-Aware scheduling. Integr. 70: 10-20 (2020) - [c203]Gereon Führ, Ahmed Hallawa, Rainer Leupers, Gerd Ascheid, Juan Fernando Eusse:
3D Optimisation of Software Application Mappings on Heterogeneous MPSoCs. ARCS 2020: 56-68 - [c202]Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Rainer Leupers, Sascha Kegreiß:
Scaling Logic Locking Schemes to Multi-module Hardware Designs. ARCS 2020: 138-152 - [c201]Andre Guntoro, Cecilia De la Parra, Farhad Merchant, Florent de Dinechin, John L. Gustafson, Martin Langhammer, Rainer Leupers, Sangeeth Nambiar:
Next Generation Arithmetic for Edge Computing. DATE 2020: 1357-1365 - [c200]Lukas Jünger, Jan Luca Malte Bölke, Stephan Tobies, Rainer Leupers, Andreas Hoffmann:
ARM-on-ARM: Leveraging Virtualization Extensions for Fast Virtual Platforms. DATE 2020: 1508-1513 - [c199]Milan Copic, Rainer Leupers, Gerd Ascheid:
Modelling Machine Learning Components for Mapping and Scheduling of AUTOSAR Runnables. ISSRE 2020: 127-137 - [c198]Lukas Jünger, Niko Zurstraßen, Tim Kogel, Holger Keding, Rainer Leupers:
AMAIX: A Generic Analytical Model for Deep Learning Accelerators. SAMOS 2020: 36-51 - [c197]Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Rainer Leupers, Massimiliano Giacometti, Sascha Kegreiß:
A secure hardware-software solution based on RISC-V, logic locking and microkernel. SCOPES 2020: 62-65 - [i9]Riya Jain, Niraj N. Sharma, Farhad Merchant, Sachin B. Patkar, Rainer Leupers:
CLARINET: A RISC-V Based Framework for Posit Arithmetic Empiricism. CoRR abs/2006.00364 (2020) - [i8]Andreas Bytyn, René Ahlsdorf, Rainer Leupers, Gerd Ascheid:
Dataflow Aware Mapping of Convolutional Neural Networks Onto Many-Core Platforms With Network-on-Chip Interconnect. CoRR abs/2006.12274 (2020) - [i7]Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Harshit Srivastava, Ahmed Hallawa, Rainer Leupers:
Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach. CoRR abs/2011.10389 (2020) - [i6]Jan Moritz Joseph, Ananda Samajdar, Lingjun Zhu, Rainer Leupers, Sung Kyu Lim, Thilo Pionteck, Tushar Krishna:
Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators. CoRR abs/2012.12563 (2020)
2010 – 2019
- 2019
- [j42]Gereon Führ, Seyit Halil Hamurcu, Diego Pala, Thomas Grass, Rainer Leupers, Gerd Ascheid, Juan Fernando Eusse:
Automatic Energy-Minimized HW/SW Partitioning for FPGA-Accelerated MPSoCs. IEEE Embed. Syst. Lett. 11(3): 93-96 (2019) - [j41]Gereon Führ, Ahmed Hallawa, Rainer Leupers, Gerd Ascheid, Juan Fernando Eusse:
Multi-objective optimisation of software application mappings on heterogeneous MPSoCs: TONPET versus R2-EMOA. Integr. 69: 50-61 (2019) - [c196]Manuel Strobel, Gereon Führ, Martin Radetzki, Rainer Leupers:
Combined MPSoC Task Mapping and Memory Optimization for Low-Power. APCCAS 2019: 121-124 - [c195]Milan Copic, Rainer Leupers, Gerd Ascheid:
Efficient sporadic task handling in parallel AUTOSAR applications using runnable migration. ASP-DAC 2019: 603-608 - [c194]Gereon Onnebrink, Ahmed Hallawa, Rainer Leupers, Gerd Ascheid, Awaid-Ud-Din Shaheen:
A heuristic for multi objective software application mappings on heterogeneous MPSoCs. ASP-DAC 2019: 609-614 - [c193]Dominik Sisejkovic, Farhad Merchant, Rainer Leupers, Gerd Ascheid, Sascha Kegreiss:
Inter-Lock: Logic Encryption for Processor Cores Beyond Module Boundaries. ETS 2019: 1-6 - [c192]Dominik Sisejkovic, Farhad Merchant, Rainer Leupers, Gerd Ascheid, Sascha Kegreiss:
Control-Lock: Securing Processor Cores Against Software-Controlled Hardware Trojans. ACM Great Lakes Symposium on VLSI 2019: 27-32 - [c191]Sebastian Birke, Dominik Auras, Tobias Piwczyk, Robin Mahlke, Nikolas Alberti, Rainer Leupers, Gerd Ascheid:
VLSI Architectures for ORVD Trellis based MIMO Detection. ICNC 2019: 983-989 - [c190]Andreas Bytyn, Rainer Leupers, Gerd Ascheid:
An Application-Specific VLIW Processor with Vector Instruction Set for CNN Acceleration. ISCAS 2019: 1-5 - [c189]Lukas Jünger, Jan Henrik Weinstock, Rainer Leupers, Gerd Ascheid:
Fast SystemC Processor Models with Unicorn. RAPIDO 2019: 2:1-2:6 - [c188]Dominik Sisejkovic, Farhad Merchant, Rainer Leupers:
Protecting the Integrity of Processor Cores with Logic Encryption. SoCC 2019: 424-425 - [c187]Dominik Sisejkovic, Farhad Merchant, Rainer Leupers, Gerd Ascheid, Volker Kiefer:
A Critical Evaluation of the Paradigm Shift in the Design of Logic Encryption Algorithms. VLSI-DAT 2019: 1-4 - [c186]Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers:
A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-Design. VLSID 2019: 64-69 - [c185]Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers:
Applying Modified Householder Transform to Kalman Filter. VLSID 2019: 431-436 - [i5]Andreas Bytyn, Rainer Leupers, Gerd Ascheid:
An Application-Specific VLIW Processor with Vector Instruction Set for CNN Acceleration. CoRR abs/1904.05106 (2019) - 2018
- [c184]Robert Lajos Bücs, Rainer Leupers, Gerd Ascheid:
Multi-Scale Multi-Domain Co-Simulation for Rapid ADAS Prototyping. APCCAS 2018: 532-535 - [c183]Jan Henrik Weinstock, Robert Lajos Bücs, Florian Walbroel, Rainer Leupers, Gerd Ascheid:
AMVP - a high performance virtual platform using parallel systemC for multicore ARM architectures: work-in-progress. CODES+ISSS 2018: 13 - [c182]Robert Lajos Bücs, Maximilian Fricke, Rainer Leupers, Gerd Ascheid, Stephan Tobies, Andreas Hoffmann:
OHEX: OS-aware hybridization techniques for accelerating MPSoC full-system simulation. DATE 2018: 281-284 - [c181]Rohit Chaurasiya, John L. Gustafson, Rahul Shrestha, Jonathan Neudorfer, Sangeeth Nambiar, Kaustav Niyogi, Farhad Merchant, Rainer Leupers:
Parameterized Posit Arithmetic Hardware Generator. ICCD 2018: 334-341 - [c180]Dominik Auras, Sebastian Birke, Rainer Leupers, Gerd Ascheid:
Reducing the Computational Complexity of ORVD-Trellis Search Based MIMO Detection. ICNC 2018: 315-321 - [c179]Robert Lajos Bücs, Marcel Heistermann, Rainer Leupers, Gerd Ascheid:
Multi-Scale Code Generation for Simulation-Driven Rapid ADAS Prototyping: the SMELT Approach. ICVES 2018: 1-8 - [c178]Sebastian Birke, Wei-Jhe Chen, Gaojian Wang, Dominik Auras, Chung-An Shen, Rainer Leupers, Gerd Ascheid:
VLSI implementation of channel estimation for millimeter wave beamforming training. LASCAS 2018: 1-4 - [c177]Koen De Bosschere, Rainer Leupers:
HiPEAC compilation architecture. MECO 2018: 13 - [c176]Gereon Onnebrink, Rainer Leupers, Gerd Ascheid:
ESL Black Box Power Estimation: Automatic Calibration for IEEE UPF 3.0 Power Models. RAPIDO 2018: 1:1-1:6 - [c175]Dominik Sisejkovic, Rainer Leupers, Gerd Ascheid, Simon Metzner:
A Unifying logic encryption security metric. SAMOS 2018: 179-186 - [c174]Robert Lajos Bücs, Pramod Lakshman, Jan Henrik Weinstock, Florian Walbroel, Rainer Leupers, Gerd Ascheid:
A Multi-domain Co-simulation Ecosystem for Fully Virtual Rapid ADAS Prototyping. SMARTGREENS/VEHITS (Selected Papers) 2018: 181-201 - [c173]Robert Lajos Bücs, Pramod Lakshman, Jan Henrik Weinstock, Florian Walbroel, Rainer Leupers, Gerd Ascheid:
Fully Virtual Rapid ADAS Prototyping via a Joined Multi-domain Co-simulation Ecosystem. VEHITS 2018: 59-69 - [i4]Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers:
Efficient Realization of Givens Rotation through Algorithm-Architecture Co-design for Acceleration of QR Factorization. CoRR abs/1803.05320 (2018) - 2017
- [j40]Miguel Angel Aguilar, Juan Fernando Eusse, Projjol Ray, Rainer Leupers, Gerd Ascheid, Weihua Sheng, Prashant Sharma:
Towards Parallelism Extraction for Heterogeneous Multicore Android Devices. Int. J. Parallel Program. 45(6): 1592-1624 (2017) - [c172]Miguel Angel Aguilar, Abhishek Aggarwal, Awaid Shaheen, Rainer Leupers, Gerd Ascheid, Jerónimo Castrillón, Liam Fitzpatrick:
Multi-grained performance estimation for MPSoC compilers: work-in-progress. CASES 2017: 14:1-14:2 - [c171]Miguel Angel Aguilar, Rainer Leupers, Gerd Ascheid, Nikolaos Kavvadias, Liam Fitzpatrick:
Schedule-aware loop parallelization for embedded MPSoCs by exploiting parallel slack. DATE 2017: 1237-1240 - [c170]María H. Auras-Rodríguez, Anthony Zimmermann, Gerd Ascheid, Rainer Leupers:
Using PEGs for Automatic Extraction of Memory Access Descriptions to Support Data-Parallel Pattern Recognition. PARMA-DITAM@HiPEAC 2017: 13-18 - [c169]Andreas Bytyn, Jannik Springer, Rainer Leupers, Gerd Ascheid:
VLSI implementation of LS-SVM training and classification using entropy based subset-selection. ISCAS 2017: 1-4 - [c168]Robert Lajos Bücs, Juan Sebastian Reyes Aristizabal, Rainer Leupers, Gerd Ascheid:
Multi-level vehicle dynamics modeling and export for ADAS prototyping in a 3D driving environment. ITSC 2017: 1-8 - [c167]Jan Henrik Weinstock, Rainer Leupers, Gerd Ascheid:
Accelerating MPSoC Simulation Using Parallel SystemC and Processor Sleep Models. RAPIDO 2017: 2 - [c166]Miguel Angel Aguilar, Rainer Leupers, Gerd Ascheid, Juan Fernando Eusse:
Extraction of recursion level parallelism for embedded multicore systems. SAMOS 2017: 154-162 - [c165]Gereon Onnebrink, Florian Walbroel, Jonathan Klimt, Rainer Leupers, Gerd Ascheid, Luis Gabriel Murillo, Stefan Schürmans, Xiaotao Chen, YwhPyng Harn:
DVFS-enabled power-performance trade-off in MPSoC SW application mapping. SAMOS 2017: 196-202 - [p4]Rainer Leupers, Miguel Angel Aguilar, Juan Fernando Eusse, Jerónimo Castrillón, Weihua Sheng:
MAPS: A Software Development Environment for Embedded Multicore Applications. Handbook of Hardware/Software Codesign 2017: 917-949 - 2016
- [j39]Andres Goens, Jerónimo Castrillón, Maximilian Odendahl, Rainer Leupers:
An optimal allocation of memory buffers for complex multicore platforms. J. Syst. Archit. 66-67: 69-83 (2016) - [j38]Pier Stanislao Paolucci, Andrea Biagioni, Luis Gabriel Murillo, Frédéric Rousseau, Lars Schor, Laura Tosoratto, Iuliana Bacivarov, Robert Lajos Bücs, Clément Deschamps, Ashraf El Antably, Roberto Ammendola, Nicolas Fournel, Ottorino Frezza, Rainer Leupers, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Elena Pastorelli, Devendra Rai, Davide Rossetti, Francesco Simula:
Dynamic many-process applications on many-tile embedded systems and HPC clusters: The EURETILE programming environment and execution platforms. J. Syst. Archit. 69: 29-53 (2016) - [j37]Daniel Günther, Rainer Leupers, Gerd Ascheid:
A Scalable, Multimode SVD Precoding ASIC Based on the Cyclic Jacobi Method. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(8): 1283-1294 (2016) - [j36]Luis Gabriel Murillo, Robert Lajos Bücs, Rainer Leupers, Gerd Ascheid:
MPSoC Software Debugging on Virtual Platforms via Execution Control with Event Graphs. ACM Trans. Embed. Comput. Syst. 16(1): 7:1-7:25 (2016) - [j35]Stefan Schürmans, Gereon Onnebrink, Rainer Leupers, Gerd Ascheid, Xiaotao Chen:
Frequency-Aware ESL Power Estimation for ARM Cortex-A9 Using a Black Box Processor Model. ACM Trans. Embed. Comput. Syst. 16(1): 26:1-26:26 (2016) - [j34]Jan Henrik Weinstock, Luis Gabriel Murillo, Rainer Leupers, Gerd Ascheid:
Parallel SystemC Simulation for ESL Design. ACM Trans. Embed. Comput. Syst. 16(1): 27:1-27:25 (2016)