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ORCID11th Asia-Pacific Computer Systems Architecture Conference 2006: Shanghai, China
- Chris R. Jesshope, Colin Egan:
Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings. Lecture Notes in Computer Science 4186, Springer 2006, ISBN 3-540-40056-7 - Guang R. Gao:
The Era of Multi-core Chips -A Fresh Look on Software Challenges. 1 - Alexander V. Shafarenko:
Streaming Networks for Coordinating Data-Parallel Programs (Position Statement). 2-5 - Mariusz Bajger
, Amos Omondi:
Implementations of Square-Root and Exponential Functions for Large FPGAs. 6-23 - Sung Woo Chung, Kevin Skadron:
Using Branch Prediction Information for Near-Optimal I-Cache Leakage. 24-37 - Jing Du, Xuejun Yang, Guibin Wang, Fujiang Ao:
Scientific Computing Applications on the Imagine Stream Processor. 38-51 - Haakon Dybdahl, Per Stenström:
Enhancing Last-Level Cache Performance by Block Bypassing and Early Miss Determination. 52-66 - Rao Fu, Jiwei Lu, Antonia Zhai, Wei-Chung Hsu:
A Study of the Performance Potential for Dynamic Instruction Hints Selection. 67-80 - Jorrit N. Herder, Herbert Bos, Ben Gras, Philip Homburg, Andrew S. Tanenbaum:
Reorganizing UNIX for Reliability. 81-94 - Ching-Hsien Hsu, Ming-Yuan Own, Kuan-Ching Li:
Critical-Task Anticipation Scheduling Algorithm for Heterogeneous and Grid Computing. 95-108 - Dandan Huan, Zusong Li, Weiwu Hu, Zhiyong Liu:
Processor Directed Dynamic Page Policy. 109-122 - Huizhan Yi, Juan Chen, Xuejun Yang:
Static WCET Analysis Based Compiler-Directed DVS Energy Optimization in Real-Time Applications. 123-136 - Hae-Duck Joshua Jeong, Jong-Suk Ruth Lee:
A Study on Transformation of Self-similar Processes with Arbitrary Marginal Distributions. 137-146 - Chris R. Jesshope:
muTC - An Intermediate Language for Programming Chip Multiprocessors. 147-160 - Lih Wen Koh, Oliver Diessel:
Functional Unit Chaining: A Runtime Adaptive Architecture for Reducing Bypass Delays. 161-174 - Lian Li, Jingling Xue:
Trace-Based Data Cache Leakage Reduction at Link Time. 175-188 - Shih-Wei Liao:
Parallelizing User-Defined and Implicit Reductions Globally on Multiprocessors. 189-202 - Luke Macpherson:
Overload Protection for Commodity Network Appliances. 203-218 - Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki J. Murakami, Mehdi Sedighi, Koji Inoue:
An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit. 219-230 - Arata Shinozaki, Masatoshi Shima, Minyi Guo, Mitsunori Kubo:
A High Performance Simulator System for a Multiprocessor System Based on a Multi-way Cluster. 231-243 - Kyriakos Stavrou, Pedro Trancoso, Paraskevas Evripidou:
Hardware Budget and Runtime System for Data-Driven Multithreaded Chip Multiprocessor. 244-259 - Feilong Tang, Minglu Li, Chuliang Weng, Chongqing Zhang, Wenzhe Zhang, Hongyu Huang, Yi Wang:
Combining Wireless Sensor Network with Grid for Intelligent City Traffic. 260-269 - Xiaofeng Wu, Vassilios A. Chouliaras, José L. Núñez-Yáñez, Roger Goodall, Tanya Vladimirova:
A Novel Processor Architecture for Real-Time Control. 270-280 - Jun Xia, Li Luo, Xuejun Yang:
A 0-1 Integer Linear Programming Based Approach for Global Locality Optimizations. 281-294 - Kang Yi, Kyeong-Hoon Jung, Shih-Yang Cheng, Young-Hwan Park, Fadi J. Kurdahi, Ahmed M. Eltawil:
Design and Analysis of Low Power Image Filters Toward Defect-Resilient Embedded Memories for Multimedia SoCs. 295-308 - Takashi Yokota, Kanemitsu Ootsu, Fumihito Furukawa, Takanobu Baba:
Entropy Throttling: A Physical Approach for Maximizing Packet Mobility in Interconnection Networks. 309-322 - Ming Z. Zhang, Li Tao, Ming-Jung Seow, Vijayan K. Asari:
Design of an Efficient Flexible Architecture for Color Image Enhancement. 323-336 - Yawen Chen, Hong Shen, Haibo Zhang:
Hypercube Communications on Optical Chordal Ring Networks with Chord Length of Three. 337-343 - Yongran Chen, Xingyun Qi, Yue Qian, Wenhua Dou:
PMPS(3): A Performance Model of Parallel Systems. 344-350 - Abhinav Das, Rao Fu, Antonia Zhai, Wei-Chung Hsu:
Issues and Support for Dynamic Register Allocation. 351-358 - Jianjun Guo, Kui Dai, Zhiying Wang:
A Heterogeneous Multi-core Processor Architecture for High Performance Computing. 359-365 - Michael Hicks, Colin Egan, Bruce Christianson, Patrick Quick:
Reducing the Branch Power Cost in Embedded Processors Through Static Scheduling, Profiling and SuperBlock Formation. 366-372 - Sun-Yuan Hsieh:
Fault-Free Pairwise Independent Hamiltonian Paths on Faulty Hypercubes. 373-379 - Hsien-Jone Hsieh, Dyi-Rong Duh:
Constructing Node-Disjoint Paths in Enhanced Pyramid Networks. 380-386 - Sheng-Kai Hung, Yarsun Hsu:
Striping Cache: A Global Cache for Striped Network File System. 387-393 - Yi Jiang, Guangtao Xue, Minglu Li, Jinyuan You:
DTuplesHPC: Distributed Tuple Space for Desktop High Performance Computing. 394-400 - Zhentao Li, Shuming Chen, Zhao-Liang Li, Conghua Lei:
The Algorithm and Circuit Design of a 400MHz 16-Bit Hybrid Multiplier. 401-408 - Peng Li, Dongsheng Wang, Songliu Guo, Tao Tian, Weimin Zheng:
Live Range Aware Cache Architecture. 409-415 - Jason M. McGuiness, Colin Egan, Bruce Christianson, Guang Gao:
The Challenges of Efficient Code-Generation for Massively Parallel Architectures. 416-422 - Kunio Okuda, Siang Wun Song, Marcos Tatsuo Yamamoto:
Reliable Systolic Computing Through Redundancy. 423-429 - Yantao Pan, Xicheng Lu, Peidong Zhu, Shen Ma:
A Diversity-Controllable Genetic Algorithm for Optimal Fused Traffic Planning on Sensor Networks. 430-436 - Biju K. Raveendran, Sundar Balasubramaniam, K. Durga Prasad, S. Gurunarayanan:
A Context-Switch Reduction Heuristic for Power-Aware Off-Line Scheduling. 437-444 - Soong Hyun Shin, Sung Woo Chung, Chu Shik Jhon:
On the Reliability of Drowsy Instruction Caches. 445-451 - Kang Sun, Lingdi Ping, Jiebing Wang, Zugen Liu, Xuezeng Pan:
Design of a Reconfigurable Cryptographic Engine. 452-458 - Caixia Sun, Hong-Wei Tang, Minxuan Zhang:
Enhancing ICOUNT2.8 Fetch Policy with Better Fairness for SMT Processors. 459-465 - Himanshu Thapliyal, M. B. Srinivas:
The New BCD Subtractor and Its Reversible Logic Implementation. 466-472 - Tianzhou Chen, Wei Hu, Yi Lian:
Power-Efficient Microkernel of Embedded Operating System on Chip. 473-479 - Lucian N. Vintan, Arpad Gellert, Adrian Florea, Marius Oancea, Colin Egan:
Understanding Prediction Limits Through Unbiased Branches. 480-487 - Dong Wang, Xiao Hu, Shuming Chen, Yang Guo:
Bandwidth Optimization of the EMCI for a High Performance 32-bit DSP. 488-494 - Lei Wang, Zhiping Chen:
Research on Petersen Graphs and Hyper-cubes Connected Interconnection Networks. 495-501 - Lei Wang, Zhiying Wang, Kui Dai:
Cycle Period Analysis and Optimization of Timed Circuits. 502-508 - Haixia Wang, Dongsheng Wang, Peng Li:
Acceleration Techniques for Chip-Multiprocessor Simulator Debug. 509-515 - Meiling Wang, Lei Liu:
A DDL-Based Software Architecture Model. 516-522 - Chia-Lin Yang, Shun-Ying Wang, Yi-Jung Chen:
Branch Behavior Characterization for Multimedia Applications. 523-530 - Mei Wen, Nan Wu, Changqing Xun, Wei Wu, Chunyuan Zhang:
Optimization and Evaluating of StreamYGX2 on MASA Stream Processor. 531-537 - Kenneth M. Wilson, Philip Machanick:
SecureTorrent: A Security Framework for File Swarming. 538-544 - Nan Wu, Mei Wen, Ju Ren, Yi He, Chunyuan Zhang:
Register Allocation on Stream Processor with Local Register File. 545-551 - Xiaofeng Wu, Tanya Vladimirova:
A Self-reconfigurable System-on-Chip Architecture for Satellite On-Board Computer Maintenance. 552-558 - Xiaobo Yan, Xuejun Yang, Pu Wen:
Compile-Time Thread Distinguishment Algorithm on VIM-Based Architecture. 559-566 - Jinhui Xu, Guiming Wu, Yong Dou, Yazhuo Dong:
Designing a Coarse-Grained Reconfigurable Architecture Using Loop Self-Pipelining. 567-573 - Hoon-Mo Yang, Gi-Ho Park, Shin-Dug Kim:
Low-Power Data Cache Architecture by Address Range Reconfiguration for Multimedia Applications. 574-580 - ChangRyul Yun, YoungHwan Bae, HanJin Cho, KyoungSon Jhang:
Automatic Synthesis of Interface Circuits from Simplified IP Interface Protocols. 581-587 - Chengyi Zhang, Hongwei Zhou, Minxuan Zhang, Zuocheng Xing:
An Architectural Leakage Power Reduction Method for Instruction Cache in Ultra Deep Submicron Microprocessors. 588-594 - Wenhong Zhao, Feng Xia:
An Efficient Approach to Energy Saving in Microcontrollers. 595-601
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